Si–Ge based vertical tunnel field-effect transistor of junction-less structure with improved sensitivity using dielectric modulation for biosensing applications

A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.

Flexible multi-level quasi-volatile memory based on organic vertical transistor

Driven by important megatrends such as cloud computing,artificial intelligence,and the Internet of Things,as a device used to store programs and data in computing systems,memory is struggling to catch up with the explosive growth of data and bandwidth requirements in the system.However,the storage wair between non-volatile memory and volatile memory retards the further improvement of modern memory computing systems.Herein,a quasi-volatile transistor memory based on organic polymer/perovskite quantum dot blend was fabricated using the vertical transistor configuration.Contributing to vertical structure and appropriate doping ratio of blend film,the quasi-volatile memory device displayed 1,560 times longer data retention time(>100 s)with respect to the dynamic random access memory and fast data programming speed(20 ps)in which was far more quickly than that of other organic non-volatile memories to fill the gap between volatile and non-volatile memories.Moreover,the device retention characteristics could be further promoted under the photoelectric synergistic stimulation,which also provided the possibility to reduce electric writing condition.Furthermore,the quasi-volatile memory device showed good electrical performance under bending conditions.This work provides a simple solution to fabricate multi-level quasi-volatile memory,which opens up a whole new avenue of"universal memory"and lays a solid foundation for low power and flexible random access memory devices.

Polymer nanowire vertical transistors

By utilizing poly（3-hexylthiophene） （P3HT） polymer nanowires with diameters of -15 nm as the vertical channel material, a polymer nanowire vertical transistor has been demonstrated for the first time. The P3HT nanowires were characterized by absorption spectroscopy and scanning electron microscopy. A saturated output current was created by increasing the thickness of the polymer layers between the electrodes through several spin-coating cycles of the polymer nanowires prepared in a marginal solvent. The carrier mobility was also increased through utilization of polymer nanowires with strong interchain interactions. By introducing a small hole injection barrier between the emitter and semiconducting polymer, an on/off current ratio of 1,500 was obtained. The operating voltage is less than 2 V.

Design consideration and fabrication of 1.2-kV 4H-SiC trenched-and-implanted vertical junction field-effect transistors

We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.

Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology

Three-dimensional(3D)vertical architecture transistors represent an important technological pursuit,which have distinct advantages in device integration density,operation speed,and power consumption.However,the fabrication processes of such 3D devices are complex,especially in the interconnection of electrodes.In this paper,we present a novel method which combines suspended electrodes and focused ion beam(FIB)technology to greatly simplify the electrodes interconnection in 3D devices.Based on this method,we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al_(2)O_(3) gate-oxide both grown by atomic layer deposition.Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires,which avoid cumbersome steps in the traditional 3D structure fabrication technology.Both single pillar and arrays devices show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 106 and a low threshold voltage around 0 V.The ON-current of the 2×2 pillars vertical channel transistor was 1.2μA at the gate voltage of 3 V and drain voltage of 2 V,which can be also improved by increasing the number of pillars.Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.

Application of graphene vertical field effect to regulation of organic light-emitting transistors

The luminescence intensity regulation of organic light-emitting transistor(OLED)device can be achieved effectively by the combination of graphene vertical field effect transistor(GVFET)and OLED.In this paper,we fabricate and characterize the graphene vertical field-effect transistor with gate dielectric of ion-gel film,confirming that its current switching ratio reaches up to 102.Because of the property of high light transmittance in ion-gel film,the OLED device prepared with graphene/PEDOT:PSS as composite anode exhibits good optical properties.We also prepare the graphene vertical organic light-emitting field effect transistor(GVOLEFET)by the combination of GVFET and graphene OLED,analyzing its electrical and optical properties,and confirming that the luminescence intensity can be significantly changed by regulating the gate voltage.

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.