A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a ...A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.展开更多
In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture...In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.展开更多
基金Supported by the National Natural Science Foundation of China(No.60972126)the Joint Funds of the National Natural Science Foundation of China(No.U0935002/L05)+1 种基金the Beijing Municipal Natural Science Foundation(No.4102060)the State Key Program of the National Natural Science of China(No.61032007)
文摘A runtime reconfigurable very-large-scale integration （VLSI） architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scal- ing is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling ap- plications and also verified by many widely acknowledged image quality measures. The reconfigu- rable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array （FPGA） devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.
文摘In order to develop the core chip supporting binocular stereo displays for head mounted display （HMD） and glasses-TV, a very large scale integrated （VISI） design scheme is proposed by using a pipeline architecture for 3D display processing chip （HMD100）. Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation, and their hardware implementations which improve the image quality are presented. The proposed HMD100 chip is verified by the field-programmable gate array （FPGA）. As one of innovative and high integration SoC chips, HMD100 is designed by a digital and analog mixed circuit. It can support binocular stereo display, has better scaling effect and integration. Hence it is applicable in virtual reality （VR）, 3D games and other microdisplay domains.
