Mechanism of improving forward and reverse blocking voltages in AlGaN/GaN HEMTs by using Schottky drain

In this paper, we demonstrate that a Schottky drain can improve the forward and reverse blocking voltages （BVs） simultaneously in A1GaN/GaN high-electron mobility transistors （HEMTs）. The mechanism of improving the two BVs is investigated by analysing the leakage current components and by software simulation. The forward BV increases from 72 V to 149 V due to the good Schottky contact morphology. During the reverse bias, the buffer leakage in the Ohmic- drain HEMT increases significantly with the increase of the negative drain bias. For the Schottky-drain HEMT, the buffer leakage is suppressed effectively by the formation of the depletion region at the drain terminal. As a result, the reverse BV is enhanced from -5 V to -49 V by using a Schottky drain. Experiments and the simulation indicate that a Schottky drain is desirable for power electronic applications.

Influence of a drain field plate on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor

In this paper, the influence of a drain field plate （FP） on the forward blocking characteristics of an AlGaN/GaN high electron mobility transistor （HEMT） is investigated. The HEMT with only a gate FP is optimized, and breakdown voltage VBR is saturated at 1085 V for gate–drain spacing LGD ≥ 8 μm. On the basis of the HEMT with a gate FP, a drain FP is added with LGD=10 μm. For the length of the drain FP LDF ≤ 2 μm, VBR is almost kept at 1085 V, showing no degradation. When LDF exceeds 2 μm, VBR decreases obviously as LDF increases. Moreover, the larger the LDF, the larger the decrease of VBR. It is concluded that the distance between the gate edge and the drain FP edge should be larger than a certain value to prevent the drain FP from affecting the forward blocking voltage and the value should be equal to the LGD at which VBR begins to saturate in the first structure. The electric field and potential distribution are simulated and analyzed to account for the decrease of VBR.

Static Induction Devices with Planar Type Buried Gate

Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented.Using this structure,it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate.The experimental results demonstrate that this structure is desirable for application in power SIDs.Its advantages are high breakdown voltage and blocking gain.

A Novel Ideal Ohmic Contact SiGeC/Si Power Diode with Graded Doping Concentration

A novel structure of ideal ohmic contact p^＋ （SiGeC）-n^- -n^＋ diodes with three-step graded doping concentration in the base region is presented, and the changing doping concentration gradient is also optimized. Using MEDICI, the physical parameter models applicable for SiGeC/Si heterojunction power diodes are given. The simulation results indicate that the diodes with graded doping concentration in the base region not only have the merit of fast and soft reverse recovery but also double reverse blocking voltage,and their forward conducting voltage has dropped to some extent,compared to the diodes with constant doping concentration in the base region. The new structure achieves a good trade-off in Qs-Vf-Ir ,and its combination of properties is superior to ideal ohmic contact diodes and conventional diodes.

A new static induction thyristor with high forward blocking voltage and excellent switching performances

A new static induction thyristor （SITH） with a strip anode region and p- buffer layer structure （SAP-B） has been successfully designed and fabricated. This structure is composed of a p- buffer layer and lightly doped n- regions embedded in the p＋-emitter. Compared with the conventional structure of a buffed-gate with a diffused source region （DSR buffed-gate）, besides the simple fabrication process, the forward blocking voltage of this SITH has been increased to 1600 V from the previous value of 1000 V, the blocking gain increased from 40 to 70, and the turn-offtime decreased from 0.8 to 0.4μs.

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

According to the avalanche ionization theory,a computer-based analysis is performed to analyze the structural parameters of single-and multiple-zone junction termination extension（JTE） structures for 4H-SiC bipolar junction transistors（BJTs） with mesa structure.The calculation results show that a single-zone JTE can yield high breakdown voltages if the activated JTE dose and the implantation width are controlled precisely and a multiple-zone JTE method can decrease the peak surface field while still maintaining a high blocking capability.The influences of the positive and negative surface or interface states on the blocking capability are also shown.These conclusions have a realistic meaning in optimizing the design of a mesa power device.

The fabrication and characterization of 4H-SiC power UMOSFETs

The fabrication of 4H-SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors（UMOSFETs） is reported in this paper.The device has a 15-μm thick drift layer with 3×10^15 cm^-3 N-type doping concentration and a 3.1μm channel length.The measured on-state source-drain current density is 65.4 A/cm^2 at Vg = 40 V and VDS = 15 V.The measured threshold voltage（Vth） is 5.5 V by linear extrapolation from the transfer characteristics.A specific on-resistance（Rsp-on） is 181 mΩ·cm^2 at Vg = 40 V and a blocking voltage（BV） is 880 V（IDS = 100 μA@880V） at Vg = 0 V.

High-voltage 4H-SiC PiN diodes with the etched implant junction termination extension

This paper presents the design and fabrication of an etched implant junction termination extension（JTE）for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices.

Insulated gate bipolar transistor with trench gate structure of accumulation channel

An accumulation channel trench gate insulated gate bipolar transistor （ACT-IGBT） is proposed. The simu- lation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm2. In contrast, the on-state voltage drops of a conventional trench gate IGBT （CT-IGBT） are 1.7 and 2.4 V at a temperature of 300 and 400 K, respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.