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A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes 被引量:1
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作者 肖磊 刘玮 杨莲兴 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第3期490-496,共7页
A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given.... A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ (random jitter) RMS of 1.25GHz data rate series output is 2. 3ps (0. 0015UI) and RJ (1 sigma) is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out. 展开更多
关键词 SERDES voltage controlled ring oscillator low jitter
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Wideband CMOS LC VCO design and phase noise analysis 被引量:1
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作者 郭雪锋 王志功 +1 位作者 李智群 唐路 《Journal of Southeast University(English Edition)》 EI CAS 2008年第4期433-436,共4页
A wideband LC cross-coupled voltage controlled oscillator(VCO) is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor(CMOS) technology. Band switching capacitors are adopted to ex... A wideband LC cross-coupled voltage controlled oscillator(VCO) is designed and realized with standard 0. 18 μm complementary metal-oxide-semiconductor(CMOS) technology. Band switching capacitors are adopted to extend the frequency tuning range, and the phase noise is optimized in the design procedure. The functional relationships between the phase noise and the transistors' width-length ratios are deduced by a linear time variant (LTV) model. The theoretical optimized parameter value ranges are determined. To simplify the calculation, the working region is split into several sub-ranges according to transistor working conditions. Thus, a lot of integrations are avoided, and the phase noise function upon the design variables can be expressed as simple proportion formats. Test results show that the DC current is 8.8 mA under a voltage supply of 1.8 V; the frequency range is 1.17 to 1.90 GHz, and the phase noise reaches - 83 dBc/Hz at a 10 kHz offset from the carrier. The chip size is 1. 2 mm × 0. 9 mm. 展开更多
关键词 voltage controlled oscillator(VCO) WIDEBAND phase noise
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A Fractional-N CMOS DPLL with Self-Calibration
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作者 刘素娟 杨维明 +2 位作者 陈建新 蔡黎明 徐东升 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第11期2085-2091,共7页
A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works... A digital phase-locked loop (DPLL) based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider. 展开更多
关键词 digital phase-locked loop phase-frequency detector SELF-CALIBRATION voltage controlled oscillator FRACTIONAL-N
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Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end
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作者 徐勇 王志功 +3 位作者 李智群 章丽 闵锐 徐光辉 《Journal of Southeast University(English Edition)》 EI CAS 2005年第3期260-262,共3页
A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency (RF) front-end is presented,and design of a voltage controlled oscillator (VCO) and dual-modulus prescaler are focused o... A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency (RF) front-end is presented,and design of a voltage controlled oscillator (VCO) and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS (complementary metal-oxide-semiconductor transistor) process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with "OR" logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period. 展开更多
关键词 BLUETOOTH frequency hopping frequency synthesizer voltage controlled oscillator (VCO) dualmodulus prescaler programmable divider
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A Low Phase Noise, Low Power and Wide Tuning Range VCO with Filtering Technique in ISM Band
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作者 Masoud Sabaghi Saeid Marjani Abbas Majdabadi 《Circuits and Systems》 2016年第2期51-57,共7页
In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems a... In this paper, a novel voltage controlled oscillator (VCO) with low phase noise, low power consumption and wide tuning range in the industrial, scientific and medical (ISM) band is proposed for communication systems applications. For improving the phase noise, filtering technique is used and VCO is designed with TSMC CMOS 0.18 μm technology and the power supply is 1.5 V. The simulation results with advanced design system (ADS) shows that phase noise in 1 MHz offset frequency from the carrier is -122 dBc/Hz and tuning range is 2 to 2.8 GHz. The power consumption of the core is 2.49 mW. 展开更多
关键词 Filtering Technique Tuning Range Phase Noise Power Consumption voltage controlled oscillators (VCO)
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A 5-GHz frequency synthesizer with constant bandwidth for low IF ZigBee transceiver applications
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作者 姜亚伟 李智群 +1 位作者 舒海涌 侯凝冰 《Journal of Southeast University(English Edition)》 EI CAS 2010年第1期6-10,共5页
A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant ac... A fully integrated integer-N frequency synthesizer is implemented.The synthesizer is designed for low intermediate frequency (IF)ZigBee transceiver applications.Techniques used to make the loop bandwidth constant across the whole output frequency range of the voltage controlled oscillator(VCO)are adopted to maintain phase noise optimization and loop stability.In-phase and quadrature(IQ)signals are generated by a 1/2 frequency divider at the output of the VCO.The synthesizer is fabricated in 0.18 μm radio frequency(RF) complementary metal oxide semiconductor transistor (CMOS)technology.The chip area is 1.7 mm2.The synthesizer is measured on wafer.It consumes totally 28.8 mW excluding output buffers from a supply voltage of 1.8 V.The measured phase noise is -110 and -122 dBc/Hz at the offset of 1 and 3 MHz from a 2.405 GHz carrier,respectively.The measured reference spur at a 2 MHz offset from a 2.405 GHz carrier is-48.2 dBc.The measured setting time of the synthesizer is about 160 μs. 展开更多
关键词 phase-locked loop phase noise auto frequency calibration ZIGBEE voltage controlled oscillator
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2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip 被引量:1
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作者 CHEN Zhi-jian CAI Min +1 位作者 HE Xiao-yong XU Ken 《Journal of Central South University》 SCIE EI CAS CSCD 2016年第9期2242-2253,共12页
A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system contr... A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2. 展开更多
关键词 auto frequency calibration phase lock loop voltage control oscillator lock time
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An efficient PSP-based model for optimized cross-coupled MOSFETs in voltage controlled oscillator
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作者 Li-heng LOU Ling-ling SUN +1 位作者 Jun LIU Hai-jun GAO 《Journal of Zhejiang University-Science C(Computers and Electronics)》 SCIE EI 2013年第3期205-213,共9页
This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP ch... This paper proposes an efficient PSP-based model for cross-coupled metal-oxide-semiconductor field-effect transistors(MOSFETs) with optimized layout in the voltage controlled oscillator(VCO).The model employs a PSP charge model to characterize the bias-dependent extrinsic capacitance instead of numerical functions with strong non-linearity.The simulation convergence is greatly improved by this method.An original scheme is developed to extract the parameters of the PSP charge model based on S-parameters measurement.The interconnection parasitics of the cross-coupled MOSFETs are modeled based on vector fitting.The model is verified with an LC VCO design,and exhibits excellent convergence during simulation.The results show improvements as high as 60.5% and 61.8% in simulation efficiency and accuracy,respectively,indicating that the proposed model better characterizes optimized cross-coupled MOSFETs in advanced radio frequency(RF) circuit design. 展开更多
关键词 Layout optimizing Modeling PSP Charge model Cross-coupled Metal-oxide-semiconductor(MOS) voltage controlled oscillator(VCO)
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A 1.2-to-1.4 GHz low-jitter frequency synthesizer for GPS application
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作者 胡正飞 HUANG Min-di ZHANG Li 《Journal of Chongqing University》 CAS 2013年第2期97-102,共6页
A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel... A fully integrated frequency synthesizer with low jitter and low power consumption in 0.18 μm CMOS (complementary metal-oxide semiconductor) technology is proposed in this paper.The frequency synthesizer uses a novel single-end gain-boosting charge pump, a differential coupled voltage controlled oscillator (VCO) and a dynamic logic phase/frequency detecor (PFD) to acquire low output jitter.The output frequency range of the frequency synthesizer is up to 1 200 MHz to 1 400 MHz for GPS (global position system) application.The post simulation results show that the phase noise of VCO is only 127.1 dBc/Hz at a 1 MHz offset and the Vp-p jitter of the frequency synthesizer output clock is 13.65 ps.The power consumption of the frequency synthesizer not including the divider is 4.8 mW for 1.8 V supply and it occupies a 0.8 mm×0.7 mm chip area. 展开更多
关键词 frequency synthesizer phase-locked loop voltage controlled oscillator phase/frequency detector charge pump
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High performance of low voltage controlled ring oscillator with reverse body bias technology
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作者 Akansha SHRIVASTAVA Anshul SAXENA Shyam AKASHE 《Frontiers of Optoelectronics》 CSCD 2013年第3期338-345,共8页
In complementary metal oxide semiconductor (CMOS) nanoscalc technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for cri... In complementary metal oxide semiconductor (CMOS) nanoscalc technology, power dissipation is becoming important metric. In this work low leakage voltage controlled ring oscillator circuit system was proposed for critical communication systems with high oscillation frequency. An ideal approach has been presented with substrate biasing technique for reduction of power consumption. The simulation have been completed using cadence virtuoso 45 nm standard CMOS technology at room temperature 27~C with supply voltage Vc^d = 0.7 V. The simulation results suggest that voltage controlled ring oscillator has characterized with efficient low power voltage controlled oscillator (VCO) in term of minimum leakage power (1.23 nW) and maximum oscilla- tion frequency (4.76 GHz) with joint positive channel metal oxide semiconductor and negative channel metal oxide semiconductor (PMOS and NMOS) reverse sub- strate bias technique. PMOS, NMOS and joint reverse body bias techniques have been compared in the presented work. 展开更多
关键词 voltage controlled oscillator (VCO) leakagepower active power oscillation frequency efficiency cadence tool
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Digitally controlled oscillator design with a variable capacitance XOR gate 被引量:2
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作者 Manoj Kumar Sandeep K.Arya Sujata Pandey 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第10期86-92,共7页
A digitally controlled oscillator(DCO) using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also pro... A digitally controlled oscillator(DCO) using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 111-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 mW,respectively, with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements. 展开更多
关键词 digital control oscillator delay cell power consumption variable capacitance voltage controlled oscillators XOR gate
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Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate
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作者 Manoj Kumar Sandeep K.Arya Sujata Pandey 《Journal of Semiconductors》 EI CAS CSCD 2012年第3期52-59,共8页
Digital controlled oscillators(DCOs) are the core of all digital phase locked loop(ADPLL) circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. T... Digital controlled oscillators(DCOs) are the core of all digital phase locked loop(ADPLL) circuits. Here,DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology.Three,four and five bit controlled DCO with NMOS,PMOS and NMOS PMOS transistor switching networks are presented.A three-transistor XNOR gate has been used as the inverter which is used as the delay cell.Delay has been controlled digitally with a switch network of NMOS and PMOS transistors.The three bit DCO with one NMOS network shows frequency variations of 1.6141-1.8790 GHz with power consumption variations 251.9224-276.8591μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229-1.8868 GHz with varying power consumption of 251.9225-278.0740μW.A six bit DCO with one NMOS switching network gave an output frequency of 1.7237-1.8962 GHz with power consumption of 251.928-278.998μW.Output frequency and power consumption results for 4 6 bit DCO circuits with one PMOS and NMOS PMOS switching network have also been presented.The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits.Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits. 展开更多
关键词 digital control oscillator delay cell power consumption voltage controlled oscillators
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IC design of low power, wide tuning range VCO in 90 nm CMOS technology 被引量:1
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作者 李竹 王志功 +2 位作者 李智群 李芹 刘法恩 《Journal of Semiconductors》 EI CAS CSCD 2014年第12期133-138,共6页
A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductanc... A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET(IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range(FTR) of 18.4%and a phase noise of –101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current. 展开更多
关键词 CMOS MICROWAVE millimeter wave IMOS varactor phase noise voltage controlled oscillators
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8.64-11.62 GHz CMOS VCO and divider in a zero-IF 802.11a/b/g WLAN and Bluetooth application
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作者 孙瑜 梅年松 +2 位作者 陆波 黄煜梅 洪志良 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第10期99-103,共5页
A fully integrated VCO and divider implemented in SMIC 0.13μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented. The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals... A fully integrated VCO and divider implemented in SMIC 0.13μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented. The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.1 1 a WLAN in 5.8 GHz band or for 802.1 1b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4, respectively. A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands. The testing results show that the VCO has a phase noise of-113 dBc @ 1 MHz offset from the cartier of 5.5 GHz by dividing VCO output by two and the VCO core consumes 3.72 mW. The figure-of-merit for the tuning-range (FOMT) of the VCO is -192.6 dBc/Hz. 展开更多
关键词 CMOS integrated circuit voltage controlled oscillators phase noise wireless LAN
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A low power CMOS VCO using inductive-biasing with high performance FoM
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作者 刘伟豪 黄鲁 《Journal of Semiconductors》 EI CAS CSCD 2016年第4期100-105,共6页
A novel voltage-controlled oscillator(VCO) topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage ga... A novel voltage-controlled oscillator(VCO) topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using timevarying phase noise theory derives closed-form symbolic formulas for the 1/f^2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 m CMOS technology. Working under a 0.3 V supply voltage with 1.2 m W power consumption, the measured phase noise of the VCO is –119.4 d Bc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an Fo M of 192.5 d Bc/Hz. 展开更多
关键词 low power inductive-biasing feedback path phase noise voltage controlled oscillators(VCO)
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A 1.0 V differential VCO in 0.13 μm CMOS technology 被引量:1
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作者 曹圣国 韩科锋 +2 位作者 谈熙 闫娜 闵昊 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第2期126-129,共4页
A differential complementary LC voltage controlled oscillator (VCO) with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS (I-MOS) capacitors and an on-chip ind... A differential complementary LC voltage controlled oscillator (VCO) with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS (I-MOS) capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 ×0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6,35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz. 展开更多
关键词 differential voltage controlled oscillator CMOS inversion-mode MOS capacitors on-chip inductors
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A Ku-band wide-tuning-range high-output-power VCO in InGaP/GaAs HBT technology 被引量:1
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作者 张金灿 张玉明 +4 位作者 吕红亮 张义门 刘博 张雷鸣 向菲 《Journal of Semiconductors》 EI CAS CSCD 2015年第6期156-160,共5页
A fully integrated Ku-band voltage controlled oscillator (VCO) is presented in an InGaP/GaAs hetero- junction bipolar transistor (HBT) technology. To achieve the wide tuning range (TR), the VCO employs a Colpitt... A fully integrated Ku-band voltage controlled oscillator (VCO) is presented in an InGaP/GaAs hetero- junction bipolar transistor (HBT) technology. To achieve the wide tuning range (TR), the VCO employs a Colpitts configuration, and the VCO simultaneously achieves high output power. The implemented VCO demonstrates an oscillation frequency range from 12.82 to 14.97 GHz, a frequency TR of 15.47%, an output power from 0.31 to 6.46 dBm, and a phase noise of -94.9 dBc/Hz at 1 MHz offset from 13.9 GHz center frequency. The VCO con- sumes 52.75 mW from 5 V supply and occupies an area of 0.81 × 0.78 mm2. Finally, the figures-of-merit for VCOs is discussed. 展开更多
关键词 voltage controlled oscillator InGaP/GaAs HBT Ku band wide tuning range high output power
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A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO 被引量:1
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作者 曹圣国 杨玉庆 +2 位作者 谈熙 闫娜 闵昊 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第8期98-103,共6页
A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mech... A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz. 展开更多
关键词 PLL frequency synthesizer differential voltage controlled oscillator phase-switching prescaler CMOS
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A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers 被引量:1
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作者 Pan Yaohua Mei Niansong +2 位作者 Chen Hu Huang Yumei Hong zhiliang 《Journal of Semiconductors》 EI CAS CSCD 2012年第1期80-85,共6页
A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the ... A low-phase-noise E-A fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 #m CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards. 展开更多
关键词 phase-locked loop loop stability analysis voltage controlled oscillation phase noise
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A wideband 0.13μm CMOS LC-VCO for IMT-advanced and UWB applications
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作者 唐欣 黄风义 +1 位作者 唐旭升 邵明驰 《Journal of Semiconductors》 EI CAS CSCD 2013年第1期83-88,共6页
This paper presents an LC voltage controlled oscillator(VCO) in a dual-band frequency synthesizer for IMT-advanced and UWB applications.The switched current source,cross-coupled pair and noise filtering technique ar... This paper presents an LC voltage controlled oscillator(VCO) in a dual-band frequency synthesizer for IMT-advanced and UWB applications.The switched current source,cross-coupled pair and noise filtering technique are adopted in this VCO design to improve the performance of the phase noise,power consumption,voltage amplitude,and tuning range.In order to achieve a wide tuning range,a reconfigurable LC tank with 4 bits switch control is adopted in the core circuit design.The size of the entire chip with pad is 1.11 0.98 mm2.The test results show that the current dissipation of the VCO at UWB and IMT-Advanced band is 3 mA and 4.5 mA in a 1.2 V supply.The tuning range of the designed VCO is 3.86-5.28 GHz and 3.14-3.88 GHz.The phase-noise at 1 MHz frequency offset from a 3.5 GHz and 4.2 GHz carrier is-123 dBc/Hz and-119 dBc/Hz,respectively. 展开更多
关键词 LC VCO voltage controlled oscillator phase noise CMOS UWB IMT-ADVANCED
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