This paper proposes an adaptive method based on fuzzy logic that utilizes data from phasor measurement units(PMUs) to assess and classify generating-side voltage trajectories. The voltage variable and its associated d...This paper proposes an adaptive method based on fuzzy logic that utilizes data from phasor measurement units(PMUs) to assess and classify generating-side voltage trajectories. The voltage variable and its associated derivatives are used as the input variables of a fuzzy-logic block. In addition, the voltage trajectory is compared with the pre-selected pilot-bus voltage to make a reliable decision about the voltage operational state. Different types of short-term voltage dynamics are considered in the proposed method. The fuzzy membership functions are determined using a systematic method that considers the current situation of the voltage trajectory. Finally, the voltage status is categorized into four classes to determine appropriate remedial actions. The proposed method is validated on a IEEE 73-bus power system in a MATLAB environment.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applie...A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.展开更多
基金supported in part by Smart/Micro Grids Research Center (SMGRC),University of Kurdistan。
文摘This paper proposes an adaptive method based on fuzzy logic that utilizes data from phasor measurement units(PMUs) to assess and classify generating-side voltage trajectories. The voltage variable and its associated derivatives are used as the input variables of a fuzzy-logic block. In addition, the voltage trajectory is compared with the pre-selected pilot-bus voltage to make a reliable decision about the voltage operational state. Different types of short-term voltage dynamics are considered in the proposed method. The fuzzy membership functions are determined using a systematic method that considers the current situation of the voltage trajectory. Finally, the voltage status is categorized into four classes to determine appropriate remedial actions. The proposed method is validated on a IEEE 73-bus power system in a MATLAB environment.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
文摘A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.
