Simulation of multiphase boost DC-DC converter with the stable control strategy

The multiphase boost DC-DC converter with stable control strategy is presented. Multi- phase boost DC-DC converter is designed for high voltage and high power applications, and could be achieved by the adjustment of voltage doubler rectifiers on the secondary side of high frequency transformers. The stable control strategy for three phase boost DC-DC converter has been utilized during simulation in this study and this strategy can be extend to N-number of phases. The stable control strategy consists of only three voltage loops, which are sufficient for appropriate and efficient operation of three phase boost DC-DC converter. With the stable control strategy, the equal power balance sharing can be obtained between input and output. The stability of control strategy has been evaluated by simulating the multiphase boost DC-DC converter for the same and mismatch turn ratios of high frequency transformers. The simulation result is good and the objective of the strategy is a- chieved.

A novel CMOS charge-pump circuit with current mode control 110mA at 2.7V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm^2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.

A high-efficiency charge pump in BCD process for implantable medical devices

This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS（BCD） technology for implantable medical devices.Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm^2.