Effects of Intrathecally Administerd NaV1.8 Antisense Oligonucleotide on the Expression of Sodium Channel mRNA in Dorsal Root Ganglion

Neuropathic pain has been hypothesized to be the result of aberrant expression and function of sodium channels at the site of injury. To investigate the effects of NaV1.8 antisense oligonucleotide on the expression of sodium channel mRNA in dorsal root ganglion （DRG） neurons in chronic neuropathic pain. 24 Sprague-Dawley rats weighing 200--260 g were anesthetized with the intraperitoneal injection of 300 mg· kg^-1 choral hydrate. The CCI model was made by loose ligation of sciatic nerve trunk by 4--0 chromic gut. The mechanical and thermal pain threshold were measured before operation and 1, 3, 5, 7, 9, 11, 13 days after operation. A PE-10 catheter was implanted in subarachnoid space at lumbar region. On the 7th postoperative day the animals were randomly divided into 4 groups. The drugs were injected intrathecally twice a day for 5 consecutive days in group 2--4. The animals were decapitated 14 days after the surgery. The L4--L6 DRG of the operated side was removed and crushed, and total RNA was extracted with Trizol reagent. The contralateral side was used as control. The change of NaV1.8 sodium channel transcripts was determined by RT-PCR. Pain threshold was significantly lowered after CCI as compared with that in control group and was elevated 3 days after antisense oligonucleotide injection. Sensory neuron specific TTX-R sodium channel NaV1.8 transcript was down-regulated after antisense oligonucleotide injection at the dosage of 45 μg as compared with that in CCI group （P〈0.01）, and it was even greater at the dosage of 90 μg. The intrathecally injected NaV1.8 antisense oligonucleotide can reduce the mechanical allodynia and thermal hyperalgesia partially by downregulating the SNS transcript expression.

Cache Memory Design for Single Bit Architecture with Different Sense Amplifiers

Most modern microprocessors have one or two levels of on-chip caches to make things run faster,but this is not always the case.Most of the time,these caches are made of static random access memory cells.They take up a lot of space on the chip and use a lot of electricity.A lot of the time,low power is more important than several aspects.This is true for phones and tablets.Cache memory design for single bit architecture consists of six transistors static random access memory cell,a circuit of write driver,and sense amplifiers(such as voltage differential sense amplifier,current differential sense amplifier,charge transfer differential sense amplifier,voltage latch sense amplifier,and current latch sense amplifier,all of which are compared on different resistance values in terms of a number of transistors,delay in sensing and consumption of power.The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34μW of power which shows that power is reduced up to 83%,77.75%reduction in the case of the current differential sense amplifier,39.62%in case of charge transfer differential sense amplifier and 50%in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture.Furthermore,power reduction techniques are applied over different blocks of cache memory architecture to optimize energy.The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078μW of power,i.e.,reduce 28%more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

Low-cost sensorless control of four-switch,brushless DC motor drive with direct back-EMF detection

We propose a position sensorless control scheme for a four-switch,three-phase brushless DC motor drive,based on the zero crossing point detection of phase back-EMF voltages using newly defined error functions(EFs). The commutation in-stants are 30° after detected zero crossing points of the EFs. Developed EFs have greater magnitude rather than phase or line voltages so that the sensorless control can work at a lower speed range. Moreover,EFs have smooth transitions around zero voltage level that reduces the commutation errors. EFs are derived from the filtered terminal voltages vao and vbo of two low-pass filters,which are used to eliminate high frequency noises for calculation of the average terminal voltages. The feasibility of the proposed sensorless control is demonstrated by simulation and experimental results.

New design of sense amplifier for EEPROM memory

We present a new sense amplifier circuit for EEPROM memory. The topology of the sense amplifier uses a voltage sensing method,having low cost and low power consumption as well as high reliability. The sense amplifier was implemented in an EEPROM realized with an SMIC 0.35-μm 2P3M CMOS embedded EEPROM process. Under the condition that the power supply is 3.3 V,simulation results showed that the charge time is 35 ns in the proposed sense amplifier,and that the maximum average current consumption during the read period is 40 μA. The novel topology allows the circuit to function with power supplies as low as 1.4 V. The sense amplifier has been implemented in 2-kb EEPROM memory for RFID tag IC applications,and has a silicon area of only 240 μm2.