An Improved Y-source Inverter with the Capability of Absorbing Bus Voltage Spike

In order to avoid the bus voltage spikes caused by leakage inductance endangering the normal operation of the inverter,based on the improved Y-source inverter,the traditional clamping structure and voltage peak absorption circuit are introduced,and a high step-up and low-voltage stress improved Y-source inverter with the capability of absorbing bus voltage spike is proposed.This topology fully utilizes the structural characteristics of the improved Y-source inverter itself,and further increases the DC-side voltage gain on the basis of ensuring the busbar voltage peak absorption capacity,while reducing the capacitor voltage stress.This paper demonstrates the superiority of the proposed topology over improved Y-source inverter topology by analyzing its working principle and voltage gain,simulation and experiment platform are constructed to perform the circuit simulation and experiment,and the correctness of the theoretical analysis of the proposed inverter and the effectiveness of the busbar voltage peak absorption capacity are verified.

A New Active Gate Driver for MOSFET to Suppress Turn-Off Spike and Oscillation

MOSFETs are widely used in power electronics converters.Due to the high di/dt and dv/dt of the MOSFET and parasitic parameters in the circuit,drain voltage spikes and oscillations will be generated during turn-off,which can affect the safety of the device and degrade the system's electromagnetic compatibility.This paper first studies the relationship between drain voltage spike and gate voltage during turn-off.Based on the effect of gate voltage on drain voltage spike,a new active gate driver that optimizes gate voltage is proposed.The proposed active gate driver detects the slope of the drain voltage and generates a positive pulse in the drain current fall phase to increase the gate voltage,thereby suppressing drain voltage spike and oscillation.In order to verify the effectiveness of the proposed active gate driver,a simulation circuit and an experimental platform are constructed and compared with the conventional gate driver.Simulation and experimental results show that the new active gate driver can effectively suppress the drain voltage spike and oscillation of MOSFETs,and can effectively reduce high-frequency EMI.

Analysis of switch-induced error voltage for automatic conversion mode change charge pumps

This paper presents an exact expression for switch-induced error voltage which would cause a spike voltage on the output capacitor of the automatic conversion mode change （ACMC） charge pumps. The spike voltage will introduce several undesired problems--large output voltage ripple, serious frequency noise and low efficiency. Some methods used for reducing the spike voltage are provided by the proposed expression. An equivalent lumped model is used for deducing the expression. The ACMC charge pump circuit has been designed in SILTERRA 0.18/xm CMOS process. The experiment results show that the value of the spike voltage can match the expression well. Compared with three different improved versions, the spike voltage caused by the switch-induced error voltage can be reduced obviously.

A driving pulse edge modulation technique and its complex programming logic devices implementation

With the continual increase in switching speed and rating of power semiconductors, the switching voltage spike becomes a serious problem. This paper describes a new technique of driving pulse edge modulation for insulated gate bipolar transistors(IGBTs). By modulating the density and width of the pulse trains, without regulating the hardware circuit, the slope of the gate driving voltage is controlled to change the switching speed. This technique is used in the driving circuit based on complex programmable logic devices(CPLDs), and the switching voltage spike of IGBTs can be restrained through software, which is easier and more flexible to adjust. Experimental results demonstrate the effectiveness and practicability of the proposed method.

Analysis of the dV/dt effect on an IGBT gate circuit in IPM

The effect ofdV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.