Physical mechanism of secondary-electron emission in Si wafers

CMOS-compatible RF/microwave devices,such as filters and amplifiers,have been widely used in wireless communication systems.However,secondary-electron emission phenomena often occur in RF/microwave devices based on silicon(Si)wafers,especially in the high-frequency range.In this paper,we have studied the major factors that influence the secondary-electron yield(SEY)in commercial Si wafers with different doping concentrations.We show that the SEY is suppressed as the doping concentration increases,corresponding to a relatively short effective escape depthλ.Meanwhile,the reduced narrow band gap is beneficial in suppressing the SEY,in which the absence of a shallow energy band below the conduction band will easily capture electrons,as revealed by first-principles calculations.Thus,the new physical mechanism combined with the effective escape depth and band gap can provide useful guidance for the design of integrated RF/microwave devices based on Si wafers.

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently,machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductormanufacturing.The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features.This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns.First,the number of defects during the actual process may be limited.Therefore,insufficient data are generated using convolutional auto-encoder(CAE),and the expanded data are verified using the evaluation technique of structural similarity index measure(SSIM).After extracting handcrafted features,a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction.Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns,the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.

Wafer map defect patterns classification based on a lightweight network and data augmentation

Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines.During the wafer testing stage,deep learning methods are widely used in wafer defect detection due to their powerful feature extraction capa-bilities.However,most of the current wafer defect patterns classification models have high complexity and slow detection speed,which are difficult to apply in the actual wafer production process.In addition,there is a data imbalance in the wafer dataset that seriously affects the training results of the model.To reduce the complexity of the deep model without affecting the wafer feature expression,this paper adjusts the structure of the dense block in the PeleeNet network and proposes a lightweight network WM‐PeleeNet based on the PeleeNet module.In addition,to reduce the impact of data imbalance on model training,this paper proposes a wafer data augmentation method based on a convolutional autoencoder by adding random Gaussian noise to the hidden layer.The method proposed in this paper has an average accuracy of 95.4%on the WM‐811K wafer dataset with only 173.643 KB of the parameters and 316.194 M of FLOPs,and takes only 22.99 s to detect 1000 wafer pictures.Compared with the original PeleeNet network without optimization,the number of parameters and FLOPs are reduced by 92.68%and 58.85%,respectively.Data augmentation on the minority class wafer map improves the average classification accuracy by 1.8%on the WM‐811K dataset.At the same time,the recognition accuracy of minority classes such as Scratch pattern and Donut pattern are significantly improved.

An Uncertainty Analysis of Downward Pressure Applied to the Wafer Based on a Flexible Airbag by a Double Side Polishing Machine

The process of wafer polishing is known to be highly demanding,and even small deviations in the processing parameters can have a significant impact on the quality of the wafers obtained.During the process of wafer polishing,maintaining a constant pressure value applied by the polishing head is essential to achieve the desired flatness of the wafer.The accuracy of the downward pressure output by the polishing head is a crucial factor in producing flat wafers.In this paper,the uncertainty component of downward pressure is calculated and its measurement uncertainty is evaluated,and a method for calculating downward pressure uncertainty traceable to international basic unit is established.Therefore,the reliability of double side polishing machine has been significantly improved.

腕关节镜下Wafer术治疗尺骨撞击综合征26例围手术期护理体会

目的探索腕关节镜下尺骨头部分磨除术(Wafe术)治疗尺骨撞击综合征的围手术期护理。方法在26例尺骨撞击综合征患者行腕关节镜下Wafer术治疗期间,实施术前心理疏导、完善准备、术后并发症的预防与观察等护理措施。结果 26例患者均顺利完成手术,术后分别出现1例引流管积血阻塞和1例尺神经浅支损伤,均经对症处理后痊愈,未发生其他严重并发症。术后2个月采用改良Mayo评分评定腕关节功能,本组优良率100.00%(26/26)。术后3个月肌力恢复均至健侧80%以上。未发生腕部疼痛及严重腕关节活动受限等后遗症。结论对尺骨撞击综合征患者实施腕关节镜下Wafer术治疗期间,全面而细致行围术期护理,有助于减少术后并发症,提升手术效果和促进腕关节功能的恢复。

A spatiotemporal signal processing technique for wafer-scale IC thermomechanical stress monitoring by an infrared camera

In this paper, we describe a new silicon-die thermal monitoring approach using spatiotemporal signal processing technique for Wafer-Scale IC thermome- chanical stress monitoring. It is proposed in the context of a wafer-scale-based (WaferICTM) rapid prototyping platform for electronic systems. This technique will be embedded into the structure of the WaferIC, and will be used as a preventive measure to protect the wafer from possible damages that can be caused by excessive thermomechanical stress. The paper also presents spatial and spatiotemporal algorithms and the experimental results from an IR images collection campaign conducted using an IR camera.

110 GHz可溯源的On-wafer GaAs基Multi-TRL校准标准件研制

设计制作了用于1~110GHzOn-wafer散射参数测试系统自校准的GaAs基Multi-TRL校准标准件。主要验证了Multi-TRL校准标准件设计的正确性;经过与国外计量标准及商用校准件比对,还验证了在频率范围1GHz^110GHz,用于Multi-TRL校准的校准标准件的准确性。

H_∞ SYNCHRONIZATION CONTROL OF LINEAR SYSTEMS AND ITS APPLICATION TO WAFER-RETICAL STAGE

For the outputs of two nth-order linear control systems to work in synchronization and meanwhile to track their commands, a H∞ synchronization control scheme is presented. In terms of two uncoupled single variable linear systems, a multivariable coupled system is established by choosing one output and the difference of the two outputs as a new output vector, so that both command tracking and synchronization properties can be demonstrated by a H∞ performance index. To improve the synchronization and tracking performance and to guarantee the system robust stability, the mixed sensitivity H∞ design methodology is adopted. The presented synchronization scheme is then extended to the case where one of the two systems include two input variables, and then applied to the position synchronization control of a wafer-retical stage. The wafer-reticle stage consists of a wafer stage, a reticle coarse stage, and a reticle fine stage. The reticle coarse stage picks up the reticle fine stage. The three stages ought to tack their commands, but synchronization between the wafer stage and the reticle fine stage must be stressed in the tracking process. In the application, by appropriately determining the weighting matrices for the sensitivity function and the complementary sensitivity function, a satisfactory H∞ synchronization controller is obtained to realize highly accurate position synchronization,and to guarantee tracking performance. The above results are verified by simulation experiments.

Formation of subsurface cracks in silicon wafers by grinding

Single-crystal silicon is an important material in the semiconductor and optical industries.However,being hard and brittle,a silicon wafer is vulnerable to subsurface cracks(SSCs)during grinding,which is detrimental to the performance and lifetime of a wafer product.Therefore,studying the formation of SSCs is important for optimizing SSC-removal processes and thus improving surface integrity.In this study,a statistical method is used to study the formation of SSCs induced during grinding of silicon wafers.The statistical results show that grinding-induced SSCs are not stochastic but anisotropic in their distributions.Generally,when grinding with coarse abrasive grains,SSCs form along the cleavage planes,primarily the{111}planes.However,when grinding with finer abrasive grains,SSCs tend to form along planes with a fracture-surface energy higher than that of the cleavage planes.These findings provide a guidance for the accurate detection of SSCs in ground silicon wafers.

Scheduling Dual-Arm Cluster Tools With Multiple Wafer Types and Residency Time Constraints

Accompanying the unceasing progress of integrated circuit manufacturing technology, the mainstream production mode of current semiconductor wafer fabrication is featured with multi-variety, small batch, and individual customization, which poses a huge challenge to the scheduling of cluster tools with single-wafer-type fabrication. Concurrent processing multiple wafer types in cluster tools, as a novel production pattern, has drawn increasing attention from industry to academia, whereas the corresponding research remains insufficient. This paper investigates the scheduling problems of dual-arm cluster tools with multiple wafer types and residency time constraints. To pursue an easy-to-implement cyclic operation under diverse flow patterns,we develop a novel robot activity strategy called multiplex swap sequence. In the light of the virtual module technology, the workloads that stem from bottleneck process steps and asymmetrical process configuration are balanced satisfactorily. Moreover, several sufficient and necessary conditions with closed-form expressions are obtained for checking the system's schedulability. Finally, efficient algorithms with polynomial complexity are developed to find the periodic scheduling, and its practicability and availability are demonstrated by the offered illustrative examples.

Modeling and Validation of Indentation Depth of Abrasive Grain into Lithium Niobate Wafer by Fixed-Abrasive Lapping

The prediction of indentation depth of abrasive grain in hydrophilic fixed-abrasive(FA)lapping is crucial for controlling material removal rate and surface quality of the work-piece being machined.By applying the theory of contact mechanics,a theoretical model of the indentation depth of abrasive grain was developed and the relationships between indentation depth and properties of contact pairs and abrasive back-off were studied.Also,the average surface roughness(Ra)of lapped wafer was approximately calculated according to the obtained indentation depth.To verify the rationality of the proposed model,a series of lapping experiments on lithium niobate(LN)wafers were carried out,whose average surface roughness Ra was measured by atomic force microscope(AFM).The experimental results were coincided with the theoretical predictions,verifying the rationality of the proposed model.It is concluded that the indentation depth of the fixed abrasive was primarily affected by the applied load,wafer micro hardness and pad Young′s modulus and so on.Moreover,the larger the applied load,the more significant the back-off of the abrasive grain.The model established in this paper is helpful to the design of FA pad and its machining parameters,and the prediction of Ra as well.

Challenges in Processing Diamond Wire Cut and Black Silicon Wafers in Large-Scale Manufacturing of High Efficiency Solar Cells

Texturing of diamond wire cut wafers using a standard wafer etch process chemistry has always been a challenge in solar cell manufacturing industry. This is due to the change in surface morphology of diamond wire cut wafers and the abundant presence of amorphous silicon content, which are introduced from wafer manufacturing industry during sawing of multi-crystalline wafers using ultra-thin diamond wires. The industry standard texturing process for multi-crystalline wafers cannot deliver a homogeneous etched silicon surface, thereby requiring an additive compound, which acts like a surfactant in the acidic etch bath to enhance the texturing quality on diamond wire cut wafers. Black silicon wafers on the other hand require completely a different process chemistry and are normally textured using a metal catalyst assisted etching technique or by plasma reactive ion etching technique. In this paper, various challenges associated with cell processing steps using diamond wire cut and black silicon wafers along with cell electrical results using each of these wafer types are discussed.

Bottleneck Identification and Prediction of Wafer Fabrication Systems in Transient States

According to theory of constraints( TOCs), the performance of a complex manufacturing system,such as a wafer fabrication system,is mainly determined by its bottleneck machine.A method of the identification and prediction of the bottleneck machine was proposed in transient states of a system. Firstly,the bottleneck index was formulated based on the workloads and the variability in wafer fabrication systems. Secondly, main factors causing the variability and their influences on the bottleneck machine in transient states of the system were analyzed and discussed. An effective bottleneck identification and prediction model was presented,which incorporated the variability and queuing theory,and took machine breakdowns and setups into considerations.Finally,the proposed bottleneck prediction method was verified by simulation experiments. Results indicate that the proposed bottleneck prediction method is feasible and effective.

Raman Back-scattering study of Damaged and Strain Subsurface Layers in GaAs Wafers

The damaged and strain subsurface layers of semi insulating(SI) GaAs substrate were characterized non destructively by Raman back scattering.The study shows that the thicknesses of the damaged and strain layers are less than 3μm.The damaged and strain layer can be removed after being etched in H 2SO 4·H 2O 2·H 2O for 1.5 min.

Disbond detection with piezoelectric wafer active sensors in RC structures strengthened with FRP composite overlays

The capability of embedded piezoelectric wafer active sensors (PWAS) to perform in-situ nondestructive evaluation (NDE) for structural health monitoring (SHM) of reinforced concrete (RC) structures strengthened with fiber reinforced polymer (FRP) composite overlays is explored. First, the disbond detection method were developed on coupon specimens consisting of concrete blocks covered with an FRP composite layer. It was found that the prescnce of a disbond crack drastically changes the electromecbanical (E/M) impedance spectrum measured at the PWAS terminals. The spectral changes depend on the distance between the PWAS and the crack tip. Second, large scale experiments were conducted on a RC beam strengthened with carbon fiber reinforced polymer (CFRP) composite overlay. The beam was subject to an acccleratcd fatigue load regime in a three-point bending configuration up to a total of807,415 cycles. During these fatigue tests, the CFRP overlay experienced disbonding beginning at about 500,000 cycles. The PWAS were able to detect the disbonding before it could be reliably seen by visual inspection. Good correlation between the PWAS readings and the position and extent of disbond damage was observed. These preliminary results demonstrate the potential of PWAS technology for SHM of RC structures strengthened with FRP composite ovcrlays.

Stability Behaviour of Monolayer Tetraether Lipids on the Amino-Silanised Silicon Wafer: Comparative Study between Langmuir-Blodgett Monolayers with Self-Assembled Monolayers

This study investigated the stability behaviour of molecular monolayer symmetric chemically modified tetraether lipids caldarchaeol-PO4 on the amino-silanised silicon wafer using Langmuir-Blodgett films, Self Assembling Monolayers (SAMs), ellipsometry, and atomic force microscopy (AFM). The monolayers of caldarchaeol-PO4 were stable on the solid surface amino-silanised silicon wafer. The organizations of molecular monolayers caldarchaeol-PO4 by Langmuir-Blodgett method and SAMs have been analyzed. The surface of pressure in Langmuir-Blodgett processing is carried out monolayers caldarchaeol-PO4 more flat island inhomogeneous. Another method of monolayers caldarchaeol-PO4 by SAMs is showed a large flat domain. Monolayers caldarchaeol-PO4 by Langmuir-Blodgett method seems to be stable and chemically resistant after washing with organic solvent and an additional treatment ultrasonification with various thickness lipids arround 2 nm to 6 nm. Conversely, monolayer caldarchaeol-PO4 by SAMs appears fewer than monolayers caldarchaeol-PO4 by Langmuir-Blodgett method, the thickness of various from 1 nm to 3 nm.

Development of Low Dark Current SiGe Near-Infrared PIN Photodetectors on 300 mm Silicon Wafers

SiGe offers a low-cost alternative to conventional infrared sensor material systems such as InGaAs, InSb, and HgCdTe for developing near-infrared (NIR) photodetector devices that do not require cooling and can operate with relatively low dark current. As a result of the significant difference in thermal expansion coefficients between germanium (Ge) and silicon (Si), tensile strain incorporated into SiGe detector devices through specialized growth processes can extend their NIR wavelength range of operation. We have utilized high throughput, large-area complementary metal-oxide semiconductor (CMOS) technology to fabricate Ge based p-i-n (PIN) detector devices on 300 mm Si wafers. The two-step device fabrication process, designed to effectively reduce the density of defects and dislocations arising during deposition that form recombination centers which can result in higher dark current, involves low temperature epitaxial deposition of Ge to form a thin p+ seed layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Phosphorus was then ion-implanted to create devices with n+ regions of various doping concentrations. Secondary ion mass spectroscopy (SIMS) has been utilized to determine the doping profiles and material compositions of the layers. In addition, electrical characterization of the I-V photoresponse of different devices from the same wafer with various n+ region doping concentrations has demonstrated low dark current levels (down to below 1 nA at -1 V bias) and comparatively high photocurrent at reverse biases, with optimal response for doping concentration of 5 × 1019 cm-3.

Surface Damage in Wire cut Silicon Wafers

The surface damage and the damage depth in wire cut silicon wafers and inner diameter (ID) cut silicon wafers were studied by means of thickness meter, scanning electron microscopy (SEM) and double crystal X ray diffractometer. The results show that the surface of wire cut silicon wafers is rougher than that of ID cut silicon wafers and the surface damage in wire cut silicon wafers is more serious than that in ID cut silicon wafers, while the damage depth in wire cut silicon wafers is smaller than that in ID cut silicon wafers. The possible reasons for the generation of surface damage in wire cut silicon wafers were also discussed.

Study on Relationship between InGaAsP/InP LPE Wafer Morphology,Interface Property and Device Characteristics

Five kinds of InGaAsP/InP heterostructure materials grown with LPE have been measured by means of Auger electronanalysis,X-ray double-crystal diffraction,selective etching and surface morphology analysis.The relation between crystalmismatch and interface property of such materials has been studied and the results could be understood in terms of the growth ki-netics at the heterojunction interface.The comparison of the characteristics of the electronic and optoelectronic devices fabricatedwith the wafers under different interface properties has been carried out.And it also has been demonstrated that the wafer surfacemorphology changes with the compositional gradation by certain relation.

Finite Element Analysis for Grinding and Lapping of Wire-sawn Silicon Wafers

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure on silicon wafer manufacturers to develop cost-effective manufacturing processes. A critical issue in wafer production is the waviness induced by wire sawing. If this waviness is not removed, it will affect wafer flatness and semiconductor performance. In practice, both lapping and grinding have been used to flatten wire-sawn wafers. Although grinding is not as effective as lapping in removing waviness, it has many other advantages over lapping (such as higher throughput, fully automatic, and more benign to environment) and has great potential to reduce manufacturing cost of silicon wafers. This paper presents a finite element analysis (FEA) study on grinding and lapping of wire-sawn silicon wafers. An FEA model is first developed to simulate the waviness deformation of wire-sawn wafers in grinding and lapping processes. It is then used to explain how the waviness is removed or reduced by lapping and grinding and why the effectiveness of grinding in removing waviness is different from that of lapping. Furthermore, the model is used to study the effects of various parameters including active-grinding-zone orientation, grinding force, waviness wavelength, and waviness height on the reduction and elimination of waviness. Finally, the results of pilot experiments to verify the model are discussed.