Physical mechanism of secondary-electron emission in Si wafers

CMOS-compatible RF/microwave devices,such as filters and amplifiers,have been widely used in wireless communication systems.However,secondary-electron emission phenomena often occur in RF/microwave devices based on silicon(Si)wafers,especially in the high-frequency range.In this paper,we have studied the major factors that influence the secondary-electron yield(SEY)in commercial Si wafers with different doping concentrations.We show that the SEY is suppressed as the doping concentration increases,corresponding to a relatively short effective escape depthλ.Meanwhile,the reduced narrow band gap is beneficial in suppressing the SEY,in which the absence of a shallow energy band below the conduction band will easily capture electrons,as revealed by first-principles calculations.Thus,the new physical mechanism combined with the effective escape depth and band gap can provide useful guidance for the design of integrated RF/microwave devices based on Si wafers.

Wafer Defect Map Pattern Recognition Based on Improved ResNet

The defect detection of wafers is an important part of semiconductor manufacturing.The wafer defect map formed from the defects can be used to trace back the problems in the production process and make improvements in the yield of wafer manufacturing.Therefore,for the pattern recognition of wafer defects,this paper uses an improved ResNet convolutional neural network for automatic pattern recognition of seven common wafer defects.On the basis of the original ResNet,the squeeze-and-excitation(SE)attention mechanism is embedded into the network,through which the feature extraction ability of the network can be improved,key features can be found,and useless features can be suppressed.In addition,the residual structure is improved,and the depth separable convolution is added to replace the traditional convolution to reduce the computational and parametric quantities of the network.In addition,the network structure is improved and the activation function is changed.Comprehensive experiments show that the precision of the improved ResNet in this paper reaches 98.5%,while the number of parameters is greatly reduced compared with the original model,and has well results compared with the common convolutional neural network.Comprehensively,the method in this paper can be very good for pattern recognition of common wafer defect types,and has certain application value.

尺骨撞击综合征研究进展

尺骨撞击综合征是导致腕关节尺侧疼痛的主要原因,它是由于腕关节尺侧结构中尺骨头、三角纤维软骨复合体、月骨、三角骨之间反复发生撞击,导致腕关节尺侧长期超负荷,影响局部血供和关节润滑液的营养障碍,最终引起一系列病理改变和临床症状的关节退行性疾病。主要临床表现为腕关节尺侧的疼痛,且随着反复强力抓握活动、前臂旋前或腕部的尺偏而逐渐加重。目前该疾病的诊断主要依靠症状、查体、影像学检查及腕关节镜检查。尺骨撞击综合征可选择保守治疗,但效果往往不佳,近年来手术仍为主要的治疗方式。手术方法主要包括尺骨短缩截骨术、Wafer术、Darrach术和Sauvé-Kapandji术等,以前2种手术方式目前最为常用。现就该疾病的诊断及治疗进展进行综述。

Wafer map defect patterns classification based on a lightweight network and data augmentation

Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines.During the wafer testing stage,deep learning methods are widely used in wafer defect detection due to their powerful feature extraction capa-bilities.However,most of the current wafer defect patterns classification models have high complexity and slow detection speed,which are difficult to apply in the actual wafer production process.In addition,there is a data imbalance in the wafer dataset that seriously affects the training results of the model.To reduce the complexity of the deep model without affecting the wafer feature expression,this paper adjusts the structure of the dense block in the PeleeNet network and proposes a lightweight network WM‐PeleeNet based on the PeleeNet module.In addition,to reduce the impact of data imbalance on model training,this paper proposes a wafer data augmentation method based on a convolutional autoencoder by adding random Gaussian noise to the hidden layer.The method proposed in this paper has an average accuracy of 95.4%on the WM‐811K wafer dataset with only 173.643 KB of the parameters and 316.194 M of FLOPs,and takes only 22.99 s to detect 1000 wafer pictures.Compared with the original PeleeNet network without optimization,the number of parameters and FLOPs are reduced by 92.68%and 58.85%,respectively.Data augmentation on the minority class wafer map improves the average classification accuracy by 1.8%on the WM‐811K dataset.At the same time,the recognition accuracy of minority classes such as Scratch pattern and Donut pattern are significantly improved.

Boosted Stacking Ensemble Machine Learning Method for Wafer Map Pattern Classification

Recently,machine learning-based technologies have been developed to automate the classification of wafer map defect patterns during semiconductormanufacturing.The existing approaches used in the wafer map pattern classification include directly learning the image through a convolution neural network and applying the ensemble method after extracting image features.This study aims to classify wafer map defects more effectively and derive robust algorithms even for datasets with insufficient defect patterns.First,the number of defects during the actual process may be limited.Therefore,insufficient data are generated using convolutional auto-encoder(CAE),and the expanded data are verified using the evaluation technique of structural similarity index measure(SSIM).After extracting handcrafted features,a boosted stacking ensemble model that integrates the four base-level classifiers with the extreme gradient boosting classifier as a meta-level classifier is designed and built for training the model based on the expanded data for final prediction.Since the proposed algorithm shows better performance than those of existing ensemble classifiers even for insufficient defect patterns,the results of this study will contribute to improving the product quality and yield of the actual semiconductor manufacturing process.

An Uncertainty Analysis of Downward Pressure Applied to the Wafer Based on a Flexible Airbag by a Double Side Polishing Machine

The process of wafer polishing is known to be highly demanding,and even small deviations in the processing parameters can have a significant impact on the quality of the wafers obtained.During the process of wafer polishing,maintaining a constant pressure value applied by the polishing head is essential to achieve the desired flatness of the wafer.The accuracy of the downward pressure output by the polishing head is a crucial factor in producing flat wafers.In this paper,the uncertainty component of downward pressure is calculated and its measurement uncertainty is evaluated,and a method for calculating downward pressure uncertainty traceable to international basic unit is established.Therefore,the reliability of double side polishing machine has been significantly improved.

Nanogrinding of SiC wafers with high flatness and low subsurface damage

Nanogrinding of SiC wafers with high flatness and low subsurface damage was proposed and nanogrinding experiments were carried out on an ultra precision grinding machine with fine diamond wheels. Experimental results show that nanogrinding can produce flatness less than 1.0μm and a surface roughness Ra of 0.42nm. It is found that nanogrinding is capable of producing much flatter SiC wafers with a lower damage than double side lapping and mechanical polishing in much less time and it can replace double side lapping and mechanical polishing and reduce the removal amount of chemical mechanical polishing.

Drop failure modes of Sn-3.0Ag-0.5Cu solder joints in wafer level chip scale package

To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.

A Diamond Electrochemical Cleaning Technique for Organic Contaminants on Silicon Wafer Surfaces

Peroxodiphosphate anion （a powerful oxidant） can be formed in a special water-based cleaning agent through an electrochemical reaction on boron-doped diamond electrodes. This electrochemical reaction was applied during the oxidation,decomposition, and removal of organic contaminations on a silicon wafer surface, and it was used as the first step in the diamond electrochemical cleaning technique （DECT）. The cleaning effects of DECT were compared with the RCA cleaning technique, including the silicon surface chemical composition that was observed with X-ray photoelectron spectroscopy and the morphology observed with atomic force microscopy. The measurement results show that the silicon surface cleaned by DECT has slightly less organic residue and lower micro-roughness,so the new technique is more effective than the RCA cleaning technique.

An Improved Angle Polishing Method for Measuring Subsurface Damage in Silicon Wafers

We present an improved angle polishing method in which the end of the cover slice near the glue layer is beveled into a thin,defect-free wedge,the straight edge of which is used as the datum for measuring the depth of subsurface damage. The bevel angle can be calculated from the interference fringes formed in the wedge. The minimum depth of the subsurface damage that can be measured by this method is a few hundred nanometers. Our results show that the method is straightforward, accurate, and convenient.

光电反馈式静电悬浮的机制研究

本文主要讨论光电反馈式静电悬浮的理论问题． 研究在静电场作用下导电悬浮体的静电感应机制和绝缘悬浮体的静电极化机理，推导出悬浮体表面的感应电荷或极化电荷的计算公式，以及作用于悬浮体上的静电悬浮力的计算公式，在理论上揭示了静电力与电极电压、电极面积、悬浮间距及悬浮体电学特性等因素之间的关系． 结果表明，导电悬浮体表面的感应电荷量比绝缘悬浮体表面的极化电荷量多，因此前者所受的静电悬浮力比后者大，但两者均可实现静电悬浮，这些结论与实验结果完全符合． 本文工作为实现静电悬浮的光电反馈控制提供了理论依据．

探针卡在芯片产业化中的应用分析

芯片产业化过程中,涉及到大量探针卡的应用,探针卡对芯片测试非常重要;根据不同的标准对探针及探针卡进行分类;针对不同应用环境,分析了探针卡的选取方法;最后给出了探针卡的存放和使用相关规范,对探针卡的设计、加工及芯片的中测测试应用具有一定的参考作用。

Effect of Rapid Thermal Annealing Ambient on Gettering Efficiency and Surface Microstructure in 300mm CZ Silicon Wafers

The effect of rapid thermal annealing （RTA） ambient on denuded zone and oxygen precipitates in Czochralski （CZ） silicon wafers is studied in this paper. N2 and a N2/NH3 mixture are used as RTA ambient. It is demonstrated that a high density of oxygen precipitates and thin denuded zone are obtained in N2/NH3 ambient,while a relatively lower density of oxygen precipitates and thicker denuded zone are observed in N2 ambient. As the RTA duration times increased, the oxygen precipitate density increased and the denuded zone depth decreased. X-ray photoelectron spectroscopy （XPS） data and atomic force microscope （AFM） results show that there RTA process,which can explain the different effect of RTA was a surface nitriding reaction during the N2/NH3 ambient ambient.

Transfer of Thin Epitaxial Silicon Films by Wafer Bonding and Splitting of Double Layered Porous Silicon for SOI Fabrication

A double layered porous silicon with different porosity is formed on a heavy doped p type Si(111) substrate by changing current density during the anodizing.Then a high quality epitaxial mono crystalline silicon film is grown on the porous silicon using an ultra high vacuum electron beam evaporator.This wafer is bonded with other silicon wafer with a thermal oxide layer at room temperature.The bonded pairs are split along the porous silicon layer during subsequent thermal annealing.Thus the epitaxial Si film is transferred to the oxidized wafer to form a silicon on insulator structure.SEM,XTEM,spreading resistance probe and Hall measurement show that the SOI structure has good structural and electrical quality.

腕关节镜下Wafer术治疗尺骨撞击综合征26例围手术期护理体会

目的探索腕关节镜下尺骨头部分磨除术(Wafe术)治疗尺骨撞击综合征的围手术期护理。方法在26例尺骨撞击综合征患者行腕关节镜下Wafer术治疗期间,实施术前心理疏导、完善准备、术后并发症的预防与观察等护理措施。结果 26例患者均顺利完成手术,术后分别出现1例引流管积血阻塞和1例尺神经浅支损伤,均经对症处理后痊愈,未发生其他严重并发症。术后2个月采用改良Mayo评分评定腕关节功能,本组优良率100.00%(26/26)。术后3个月肌力恢复均至健侧80%以上。未发生腕部疼痛及严重腕关节活动受限等后遗症。结论对尺骨撞击综合征患者实施腕关节镜下Wafer术治疗期间,全面而细致行围术期护理,有助于减少术后并发症,提升手术效果和促进腕关节功能的恢复。

法定证照“中国芯”——国产高端芯片在电子机读旅行证件中的应用

我国高度重视国家信息安全,正在落实《国家安全战略纲要》。公安应用中的证件信息安全是国家信息安全的重要组成部分,正在开展相关核心技术的国产化研究与应用。目前,在电子机读旅行证件领域开展国产专用芯片应用的时机已经成熟。首先,介绍了公安应用中的芯片应用现状,特别是电子机读旅行证件的芯片应用情况和对国产证件专用芯片的需求;其次,分析了国产证件专用芯片要开展电子机读旅行证件应用需要实现的关键技术;再次,描述了公安应用对于国产证件专用芯片的安全性要求及安全性评估方法,并介绍了第三方检测认证情况及应对安全攻击要求的芯片防护技术;最后,论述了国产证件专用芯片技术发展趋势和应用前景。

多项目晶圆概念及其版图排版规则分析

介绍两种流片方式生产的晶圆,即单项目晶圆和多项目晶圆,阐述单项目晶圆和多项目晶圆的区别,并以芯片产业化测试的角度提出了多项目晶圆在流片之前进行版图排版设计注意事项,多项目晶圆排版可根据此文建议方式灵活运用。

STUDIES OF SURFACE GRINDING TEMPERATURE AFFECTED BY DIFFERENT GRINDING WAYS OF SILICON WAFER

The surface grinding temperature of the silicon wafer ground by diamond wheels is studied.Rudimentally,the properties of the surface grinding temperature generated by two grinding methods,ground by straight and cup wheels respectively,are analyzed.In addition,considering the effects of grain size and grinding depth on surface grinding temperature during these two grinding processes,significant results and conclusions are obtained from experimental research.

Microstructure studies of the grinding damage in monocrystalline silicon wafers

The depth and nature of the subsurface damage in a silicon wafer will limit the performance of IC components. Damage microstructures of the silicon wafers ground by the #325, #600, and #2000 grinding wheels was analyzed. The results show that many microcracks, fractures, and dislocation rosettes appear in the surface and subsurface of the wafer ground by the #325 grinding wheel. No obvious microstructure change exists. The amorphous layer with a thickness of about 100 nm, microcracks, high density dislocations, and polycrystalline silicon are observed in the subsurface of the wafer ground by the #600 grinding wheel. For the wafer ground by the #2000 grinding wheel, an amorphous layer of about 30 nm thickness, a polycrystalline silicon layer, a few dislocations, and an elastic deformation layer exist. In general, with the decrease in grit size, the material removal mode changes from micro-fracture mode to ductile mode gradually.

尺骨撞击综合征诊疗进展

尺骨撞击综合征是导致腕部尺侧疼痛的重要原因之一,其病因多为尺骨阳性变异,诊断依靠症状、查体、影像学检查及腕关节镜检查。X线检查可观察到尺骨阳性变异,月骨和三角骨硬化、囊变等;MRI检查可以早期发现骨髓及软骨改变如水肿、囊变,以及三角纤维软骨复合体损伤等,灵敏度及特异度较高;腕关节镜可以直接观察到腕关节月骨偏尺侧软骨软化或损伤,发现MRI等影像学检查难以发现的早期细微病变,是诊断尺骨撞击综合征的金标准,同时镜下可进行治疗性操作。尺骨撞击综合征通常保守治疗效果有限,以手术治疗为主,手术方法主要有尺骨短缩截骨术、Wafer术、腕关节镜下清理术、桡骨截骨矫形术等。该文就尺骨撞击综合征诊断及治疗进展进行综述。