Advanced manufacturing of dielectric metadevices

Metasurfaces,composed of two-dimensional nanostructures,exhibit remarkable capabilities in shaping wavefronts,encompassing phase,amplitude,and polarization.This unique proficiency heralds a transformative paradigm shift in the domain of next-generation optics and photonics,culminating in the development of flat and ultrathin optical devices.Particularly noteworthy is the all-dielectric-based metasurface,leveraging materials such as titanium dioxide,silicon,gallium arsenide,and silicon nitride,which finds extensive application in the design and implementation of high-performance optical devices,owing to its notable advantages,including a high refractive index,low ohmic loss,and cost-effectiveness.Furthermore,the remarkable growth in nanofabrication technologies allows for the exploration of new methods in metasurface fabrication,especially through wafer-scale nanofabrication technologies,thereby facilitating the realization of commercial applications for metasurfaces.This review provides a comprehensive overview of the latest advancements in state-of-the-art fabrication technologies in dielectric metasurface areas.These technologies,including standard nanolithography[e.g.,electron beam lithography(EBL)and focused ion beam(FIB)lithography],advanced nanolithography(e.g.,grayscale and scanning probe lithography),and large-scale nanolithography[e.g.,nanoimprint and deep ultraviolet(DUV)lithography],are utilized to fabricate highresolution,high-aspect-ratio,flexible,multilayer,slanted,and wafer-scale all-dielectric metasurfaces with intricate nanostructures.Ultimately,we conclude with a perspective on current cutting-edge nanofabrication technologies.

Step-edge controlled fast growth of wafer-scale MoSe_(2)films by MOCVD

Two-dimensional(2D)transition metal dichalcogenides(TMDCs),due to their unique physical properties,have a wide range of applications in the next generation of electronics,optoelectronics,and valleytronics.Large-scale preparation of high-quality TMDCs films is critical to realize these potential applications.Here we report a study on metal-organic chemical vapor deposition(MOCVD)growth of wafer-scale MoSe_(2)films guided by the crystalline step edges of miscut sapphire wafers.We established that the nucleation density and growth rate of MoSe_(2)films were positively correlated with the step-edge density and negatively with the growth temperature.At a certain temperature,the MoSe_(2)domains on the substrate with high step-edge density grow faster than that with low density.As a result,wafer-scale and continuous MoSe_(2)films can be formed in a short duration(30 min).The MoSe_(2)films are of high crystalline quality,as confirmed by systematic Raman and photoluminescence(PL)measurements.The results provide an important methodology for the rapid growth of wafer-scale TMDCs,which may promote the application of 2D semiconductors.

Improving the device performances of two-dimensional semiconducting transition metal dichalcogenides: Three strategies

Two-dimensional(2D)semiconductors are emerging as promising candidates for the next-generation nanoelectronics.As a type of unique channel materials,2D semiconducting transition metal dichalcogenides(TMDCs),such as MoS2 and WS2,exhibit great potential for the state-of-the-art fieldeffect transistors owing to their atomically thin thicknesses,dangling-band free surfaces,and abundant band structures.Even so,the device performances of 2D semiconducting TMDCs are still failing to reach the theoretical values so far,which is attributed to the intrinsic defects,excessive doping,and daunting contacts between electrodes and channels.In this article,we review the up-to-date three strategies for improving the device performances of 2D semiconducting TMDCs:(i)the controllable synthesis of wafer-scale 2D semiconducting TMDCs single crystals to reduce the evolution of grain boundaries,(ii)the ingenious doping of 2D semiconducting TMDCs to modulate the band structures and suppress the impurity scatterings,and(iii)the optimization design of interfacial contacts between electrodes and channels to reduce the Schottky barrier heights and contact resistances.In the end,the challenges regarding the improvement of device performances of 2D semiconducting TMDCs are highlighted,and the further research directions are also proposed.We believe that this review is comprehensive and insightful for downscaling the electronic devices and extending the Moore’s law.

Wafer-scale fabrication of carbon-nanotube-based CMOS transistors and circuits with high thermal stability

Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication processes enable three-dimensional(3D)integration with logic and memory(static random access memory(SRAM),magnetic random access memory(MRAM),resistive random access memory(RRAM),etc.)to realize efficient near-memory computing.Importantly,carbon nanotube transistors require good thermal stability up to 400℃ processing temperature to be compatible with back-end-of-line(BEOL)process,which has not been previously addressed.In this work,we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity,where AlN was employed as electrostatic doping layer.The gate stack and passivation layer were optimized to realize high-quality interfaces.Specifically,we demonstrate 1-bit carbon nanotube full adders working under 250℃ with rail-to-rail outputs.