A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm^2.It achieves a sensitivity of -80 d Bm for 10^（-3）BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 m W.

A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness

This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system.A double-mode detection method,including amplitude detection and frequency detection,is proposed to reject interference and reduce false wake-ups.An improved closed-loop band-pass filter and a DC offset cancellation technique are also newly introduced to enhance the sensitivity robustness.The circuit is fabricated in TSMC 0.18μm 3.3 V CMOS technology with an area of 0.12 mm2.Measurement results show that the sensitivity is -54.5 dBm with only a±0.95 dBm variation from the 1.8 to 3.3 V power supply,and that the temperature variation of the sensitivity is±1.4 dBm from -50 to 100℃. The current consumption is 1.4 to 1.7μA under a 1.8 to 3.3 V power supply.

用于5.8GHz ETC超低功耗唤醒接收机模拟前端

基于5.8 GHz电子不停车收费系统(electronic toll collection,ETC)应用,介绍了射频收发芯片中唤醒接收机(wake-up receiver,WuR)的模拟前端电路。采用了一种共源共栅结构的射频包络检波器(RF envelop detector,RFED)并分析了其频率转换机制,利用亚阈值偏置技术,实现了高电流效率和高频率转移效率。设计了具有带通滤波特性的可编程增益放大器(PGA)、带迟滞功能的比较器以及电流基准源等子电路。电路基于TSMC 0.18μm CMOS工艺制造,占用芯片面积约为430μm×300μm。实测结果表明,在3.3 V电源供电条件下,模拟前端电路仅消耗2.5μA电流,实现了-45 dBm的唤醒接收灵敏度,满足ETC WuR的设计指标和实际应用需求。

An ultra-low-power RF transceiver for WBANs in medical applications

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks（WBANs）in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver（RX）with an ultra-low-power free-running ring oscillator and a high speed main transmitter（TX）with fast lock-in PLL.A passive wake-up receiver（WuRx）for wake-up function with a high power conversion efficiency（PCE）CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm^2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves ＋3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.