Design of a Bandgap Reference with a Wide Supply Voltage Range

An on-chip voltage reference with a wide supply voltage range is required by some applications,especially that of power management （PM） controller chips applied to telecommunication, automotive, lighting equipment, etc., when high power supply voltage is needed. Accordingly,a new bandgap reference with a wide supply voltage range is proposed. Due to the improved structure,it features a high power supply rejection ratio （PSRR） and high temperature stability. In addition, an auxiliary micro-power reference is introduced to support the sleep mode of the PM chip and reduce its standby power consumption. The auxiliary reference provides bias currents in normal mode and a 1.28V reference voltage in sleep mode to replace the main reference and save power. Simulation results show that the reference provides a reference volt- age of 1.27V,which has a 3.5mV drift over the temperature range from -20 to 120~C and 56t^V deviation over a supply voltage range from 3 to 40V. The PSRR is higher than 100dB for frequency below 10kHz. The circuit was completed in 1.5tzm BCD （Bipolar-CMOS-DMOS） technology. The experimental results show that all main expectations are achieved.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier （IA） and a cyclic analog-to-digital converter （CADC）. The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits （ENOB） of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 （including pads）. In-vitro recording was successfully carried out by the proposed frontend chip.