Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this pa...Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.展开更多
文章提出了一种有效分离并重构信号的数字化方案。信号A和信号B通过加法器叠加成信号C,对信号C进行快速傅里叶变换,再通过直接数字合成(Direct Digital Synthesizer,DDS)模块分别输出重构信号A′和重构信号B′。测试结果表明:当输入信号...文章提出了一种有效分离并重构信号的数字化方案。信号A和信号B通过加法器叠加成信号C,对信号C进行快速傅里叶变换,再通过直接数字合成(Direct Digital Synthesizer,DDS)模块分别输出重构信号A′和重构信号B′。测试结果表明:当输入信号为1时,V PP的正弦波或者三角波频率在10~100 kHz。所提方案能够有效分离出2路重构信号,重构信号无失真、无漂移,能够调节2路信号相位差。展开更多
A soil electrical conductivity(EC)measurement system based on direct digital synthesizer(DDS)and digital oscilloscope was developed.The system took the“current-voltage four-electrode method”as the design principal a...A soil electrical conductivity(EC)measurement system based on direct digital synthesizer(DDS)and digital oscilloscope was developed.The system took the“current-voltage four-electrode method”as the design principal and adopted a six-pin structure of the probe,two center pins to measure the soil EC in shallow layer,two outside pins to measure the soil EC in deep layer,and two middle pins for inputting the driving current.A signal generating circuit using DDS technology was adopted to generate sine signals,which was connected with the two middle pins.A digital oscilloscope was used to record and store the two soil output signals with noises in microseconds,which were from the two center pins and two outside pins,respectively.Then a digital bandpass filter was used to filter the soil output signals recorded by the digital oscilloscope.Compared with the traditional analog filter circuit,the digital filter could filter out the noises of all frequency except for the frequency of the excitation source.It could improve the effect of filtering and the accuracy of the soil EC measurement system.The DDS circuit could provide more stable sine signals with larger amplitudes.The use of digital oscilloscope enables us to analyze the soil output signals in microseconds and measure the soil EC more accurately.The new soil EC measurement system based on DDS and digital oscilloscope can provide a new effective tool for soil sensing in precision agriculture.展开更多
This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place ...This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.展开更多
This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order ...This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.展开更多
This paper presents a detailed description of a high-performance direct digital frequency synthesizer (DDFS) using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter RO...This paper presents a detailed description of a high-performance direct digital frequency synthesizer (DDFS) using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter ROMs structure in 0.13 μm CMOS is brought forward and implemented. The working frequency is increased by 40% compared with Yuan Ling's methodIll of implementing a segmented DAC based DDFS. It has been implemented in 0.13 μm CMOS technology. The DDFS has a resolution of 10 bits with a measured SFDR 54 dBc. Its maximum operating frequency is 1.2 GHz by using six pipelining stages. Analytical investigation of improving spectral performances by using dual-slope approximation and pipeline is also presented.展开更多
An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer ( DDS ) -driven wideband phase-locked loop (PLL) architecture which...An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer ( DDS ) -driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.展开更多
为提高移频轨道电路发码装置输出信号的质量及装置的可靠性,设计一种基于直接数字频率合成器(DDS,Direct Digital Synthesizer)芯片的发码装置。该装置由单片机直接控制DDS芯片产生移频信号,经过后级电路放大滤波后,输出到测试环线上,...为提高移频轨道电路发码装置输出信号的质量及装置的可靠性,设计一种基于直接数字频率合成器(DDS,Direct Digital Synthesizer)芯片的发码装置。该装置由单片机直接控制DDS芯片产生移频信号,经过后级电路放大滤波后,输出到测试环线上,供车载天线接收;单片机提供RS-485通信电路用来接收上位机的控制数据、有机发光二极管(OLED,Organic Light-Emitting Diode)显示屏和按键,作为便携式设备的人员操作接口。通过测试验证,该装置可精确输出ZPW-2000和FTGS这2种移频轨道电路的移频键控(FSK,Frequency-Shift Keying)调制信号,提高了输出信号的分辨率和精度,从而减小相邻轨道区段间的干扰,便于机车信号设备的解调。与既有的移频轨道电路发码装置相比,该装置具有信号质量高、结构简单、可靠性高、方便操作的优点。展开更多
电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,...电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。展开更多
文章主要介绍一种现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)控制数字频率合成器(Direct Digital Synthesizer,DDS)实现四进制移频键控(Quaternary Frequency Shift Keying,4FSK)&频率调制(Frequency Modulation,FM...文章主要介绍一种现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)控制数字频率合成器(Direct Digital Synthesizer,DDS)实现四进制移频键控(Quaternary Frequency Shift Keying,4FSK)&频率调制(Frequency Modulation,FM)调制载波的设计方案,给出技术指标参数、硬件组成框图以及信号处理流程,对4FSK的调制信号和FM信号产生的实施方法进行探讨,并对电路框图中的关键器件进行国产化设计选型。展开更多
基金Supported by National High-Technology Research and Development Plan of China (Grant No.2006AA01Z452)
文摘Amplitude quantization is one of the main sources of spurious noise frequencies in Direct Digital Frequency Synthesizers (DDFSs), which affect their application to many wireless telecommu- nication systems. In this paper, two different kinds of spurious signals due to amplitude quantization in DDFSs are exactly formulated in the time domain and detailedly compared in the frequency do- main, and the effects of the DDFS parameter variations on the spurious performance are thoroughly studied. Then the spectral properties and power levels of the amplitude-quantization spurs in the absence of phase-accumulator truncation are emphatically analyzed by waveform estimation and computer simulation, and several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.
文摘文章提出了一种有效分离并重构信号的数字化方案。信号A和信号B通过加法器叠加成信号C,对信号C进行快速傅里叶变换,再通过直接数字合成(Direct Digital Synthesizer,DDS)模块分别输出重构信号A′和重构信号B′。测试结果表明:当输入信号为1时,V PP的正弦波或者三角波频率在10~100 kHz。所提方案能够有效分离出2路重构信号,重构信号无失真、无漂移,能够调节2路信号相位差。
基金This study was supported by the Chinese National Key Research and Development Plan(2016YFD0700300-2016YFD0700304)the National Natural Science Foundation of China(31801265).
文摘A soil electrical conductivity(EC)measurement system based on direct digital synthesizer(DDS)and digital oscilloscope was developed.The system took the“current-voltage four-electrode method”as the design principal and adopted a six-pin structure of the probe,two center pins to measure the soil EC in shallow layer,two outside pins to measure the soil EC in deep layer,and two middle pins for inputting the driving current.A signal generating circuit using DDS technology was adopted to generate sine signals,which was connected with the two middle pins.A digital oscilloscope was used to record and store the two soil output signals with noises in microseconds,which were from the two center pins and two outside pins,respectively.Then a digital bandpass filter was used to filter the soil output signals recorded by the digital oscilloscope.Compared with the traditional analog filter circuit,the digital filter could filter out the noises of all frequency except for the frequency of the excitation source.It could improve the effect of filtering and the accuracy of the soil EC measurement system.The DDS circuit could provide more stable sine signals with larger amplitudes.The use of digital oscilloscope enables us to analyze the soil output signals in microseconds and measure the soil EC more accurately.The new soil EC measurement system based on DDS and digital oscilloscope can provide a new effective tool for soil sensing in precision agriculture.
文摘This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.
文摘This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 x 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.
文摘This paper presents a detailed description of a high-performance direct digital frequency synthesizer (DDFS) using optimized quarter ROMs. To improve the working frequency and spectral purity, an original quarter ROMs structure in 0.13 μm CMOS is brought forward and implemented. The working frequency is increased by 40% compared with Yuan Ling's methodIll of implementing a segmented DAC based DDFS. It has been implemented in 0.13 μm CMOS technology. The DDFS has a resolution of 10 bits with a measured SFDR 54 dBc. Its maximum operating frequency is 1.2 GHz by using six pipelining stages. Analytical investigation of improving spectral performances by using dual-slope approximation and pipeline is also presented.
基金Supported by the Fund of National Defense Industry Innova-tive Team(231)
文摘An S-band frequency synthesizer for a stepped-frequency radar is presented. This frequen- cy synthesizer is based on a direct digital synthesizer ( DDS ) -driven wideband phase-locked loop (PLL) architecture which can achieve low spurious noise and rapid frequency hopping simultaneous- ly. The mechanism of introducing high level spurs by the images of DDS digital to analog convertor (DAC) output is analyzed. A novel DDS frequency planning method is proposed to ensure low col- ored noise within the entire bandwidth. The designed output frequency range is 3. 765 -4. 085 GHz, and the step size is 5 MHz with frequency agility of less than 1 μs. Measured results demonstrate that the average spurious free dynamic range (SFDR) is about 64 dBc in a 320 MHz bandwidth.
文摘电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。
文摘文章主要介绍一种现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)控制数字频率合成器(Direct Digital Synthesizer,DDS)实现四进制移频键控(Quaternary Frequency Shift Keying,4FSK)&频率调制(Frequency Modulation,FM)调制载波的设计方案,给出技术指标参数、硬件组成框图以及信号处理流程,对4FSK的调制信号和FM信号产生的实施方法进行探讨,并对电路框图中的关键器件进行国产化设计选型。