Crosstalk and Wire Length Reduction in the Non-Manhattan Channel Routing

A novel framework for non-Manhattan channel routing considering crosstalk and wire length reduction is proposed. To handle crosstalk and wire length reduction problem, an improved non-Manhattan router in the gridded routing model is developed, and a novel rerouting algorithm based on segment-rerouting technique and layer reassignment is presented. Simulation exDeriments demonstrate that our algorithm achieves verv good results.

XGRouter： high-quality global router in X-architecture with particle swarm optimization

This paper presents a high-quality very large scale integration （VLSI） global router in X-architecture, called XGRouter, that heavily relies on integer linear pro- gramming （ILP） techniques, partition strategy and particle swarm optimization （PSO）. A new ILP formulation, which can achieve more uniform routing solution than other formu- lations and can be effectively solved by the proposed PSO is proposed. To effectively use the new ILP formulation, a partition strategy that decomposes a large-sized problem into some small-sized sub-problems is adopted and the routing re- gion is extended progressively from the most congested re- git）n. In the post-processing stage of XGRouter, maze rout- ing based on new routing edge cost is designed to further optimize the total wire length and mantain the congestion uniformity. To our best knowledge, XGRouter is the first work to use a concurrent algorithm to solve the global rout- ing problem in X-architecture. Experimental results show that XGRouter can produce solutions of higher quality than other global routers. And, like several state-of-the-art global touters, XGRouter has no overflow.

A novel interconnect optimal buffer insertion model considering the self-heating effect

Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.