Rail-to-rail op-amp with constant transconductance,SR and gain

A novel general-purpose low-voltage rail-to-rail CMOS （ complementary metal-oxide-semiconductor transistor ） operational amplifier （op-amp）is introduced, which obtains constant transconductance, slew rate and constant high gain over the entire input common mode voltage range. The proposed scheme has the potential for applications in deep submicrometer technology, as the operation of the circuit does not exclusively rely on the square-law or the linear-law of transistors. The scheme is compact and suitable for applications as VLSI cell. The rail-to- rail op-amp has been implemented in DPDM 0. 6 μm mixedsignal process. The simulations show that in the entire range of input common mode voltage, the variations in transconductance, SR and gain are 1%, 2. 3%, 1.36 dB, respectively. Based on this, the layout and tape-out are carded out. The area of layout is 0. 072 mm^2. The test results are basically consistent with the circuit simulation.

完备完全树及其在Op-Amp电路分析中的应用

介绍一种分析Op-Amp电路的拓扑公式和算法。与Mayeda算法相比,本算法不需要处理双图;也克服了完全树符号确定的困难。举例说明了该算法在电路分析中的应用。

单OP-AMP二阶低通巴特沃斯滤波器的参数选择

从减少同一种参数的数值类别出发选择阻容元件的参数

Two Simple Analog Multiplier Based Linear VCOs Using a Single Current Feedback Op-Amp

Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The workability of the presented VCOs has been demonstrated by experimental results based upon AD844 type CFOAs and AD534 type AMs.

一种高PSRR的无运放带隙基准电路

设计了一种无运放带隙基准电路,该电路采用电压自调节技术来稳定输出基准电压,并实现该带隙基准电路在较宽频率范围内的高PSRR。该基准采用无运放结构,在降低电路复杂性的同时,避免了运算放大器的失调电压对输出基准的温度系数的影响。基于0.18μm BCD工艺,在Cadence环境下仿真得到该电路在10 Hz时,PSRR为-94 dB,在1 MHz时,PSRR为-44 dB;在-40~125℃温度范围内,温度系数为4×10^(-6)/℃;包含启动电路在内,该电路静态电流约为14μA,片上面积约为0.016 mm^(2)。

无运放高阶温度补偿的基准电路设计

基于带隙基准源的工作原理以及如何提高温度特性的思想,设计了一种无运算放大器且具有新型高阶温度补偿的带隙基准电路。通过对传统带隙基准电路结构的改进,提出一种新的高阶温度补偿方法。该电路在不使用运放的情况下,分别产生较为精准的正、负温度系数电流,通过共源-共栅电流镜将负温度系数电流降阶,并对其一阶、二阶温度系数进行补偿。电路采用0.18μm CMOS工艺实现,芯片尺寸为240μm×220μm,电源抑制比(PSRR)-64dB。测试结果表明:输出基准电压均值为580.6 mV,在-45~120℃范围内温度系数为7.5×10-6/℃,整个电路的功耗为45μW。

An Accelerated Simulation Method for ELDRS of Bipolar Operational Amplifiers Using a Dose-Rate Switching Experiment

Through different dose-rate switching evaluation methods,the radiation-response rules of operational amplifiers are studied when the irradiation dose rate is switched from high to low under different radiation temperatures and total doses. The experimental results indicate that the response characteristics could be affected by the switching total doses, irradiation temperatures,and dose rates individually or together. Accelerated evaluation on the ELDRS can be realized by adopting a proper dose-rate switching method. Meanwhile, the irradiation time can also be reduced. Finally, the mechanisms of the difference between various radiation responses are analyzed.

一种无运放高电源抑制比的带隙基准设计

为满足集成电路中高电源抑制比/低温度系数的要求,设计了一款没有运放的精简的带隙电压电路。相比传统有运放结构,电路芯片面积更小且具有更低的电流损耗。并在0.5μm CMOS工艺下进行了仿真,仿真结果表明,在-40℃^+100℃温度范围内电路的温度系数为17×10-6,电源抑制比PSRR在100 k Hz以下达到-50 d B,在1 k Hz以下能达到-80 d B,而整个电路在3.3 V电压下电流损耗仅为24μA。

低电源电压超低功耗Delta-Sigma调制器

为了在低电源电压约束下实现delta-sigma模数转换器(ADC)的低功耗与高精度设计,提出基于开关型运放以及新颖DWA技术的delta-sigma调制器.其中的开关型运放仅工作于半周期相位,可以在低于1V的电源电压下正常工作,节省了系统功耗.调制器的积分器采用运放分享技术,以降低硬件开销.采用双向循环移位数据加权平均(DCS-DWA)技术,在抑制调制回路中匹配单元误差引起的非线性失真的同时消除了与输入信号相关的寄生音调,提高系统分辨率.提出的delta-sigma调制器在SMIC 0.18μm 1P6M工艺下流片,动态范围与峰值SNDR分别达94.6和92.5dB,芯片面积为0.72mm2.在0.9V电源电压下,测得系统功耗仅为56μW,品质因数(FoM)低至34.2fJ/c-step.结果表明,预期的主要设计目标均已实现.

Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...

Low-Power Operational Amplifier for Real-Time Signal Processing System of Micro Air Vehicle

A low-power complementary metal oxide semiconductor（CMOS） operational amplifier （op-amp） for real-time signal processing of micro air vehicle （MAV） is designed in this paper.Traditional folded cascode architecture with positive channel metal oxide semiconductor（PMOS） differential input transistors and sub-threshold technology are applied under the low supply voltage.Simulation results show that this amplifier has significantly low power,while maintaining almost the same gain,bandwidth and other key performances.The power required is only 0.12 mW,which is applicable to low-power and low-voltage real-time signal acquisition and processing system.

Optimizing the Stage Resolution of a 10-Bit, 50 Ms/Sec Pipelined A/D Converter &Its Impact on Speed, Power, Area, and Linearity

At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.

A High-Performance Operational Amplifier for High-Speed High-Accuracy Switch-Capacitor Cells

A high-speed high-accuracy fully differenttial operational amplifier （op-amp） is realized based on no-Miller-capacitor feedforward （NMCF） compensation scheme. In order to achieve a good phase margin, the NMCF compensation scheme uses the positive phase shift of left-half-plane （LHP） zero caused by the feedforvvard path to counteract the negative phase shift of the non-dominant pole. Compared to traditional Miller compensation method, the op-amp obtains high gain and wide band synchronously without the pole-splitting effect while saves significant chip area due to the absence of the Miller capacitor. Simulated by the 0.35 μm CMOS RF technology, the result shows that the open-loop gain of the op-amp is 118 dB with the unity gain-bandwidth （UGBW） of 1 GHz, and the phase margin is 61°while the settling time is 5.8 ns when achieving 0.01% accuracy. The op-amp is especially suitable for the front-end sample/hold （S/H） cell and the multiplying D/A converter （MDAC） module of the high-speed high-resolution pipelined A/D converters （AVCs）.

Canonic Realizations of Voltage-Controlled Floating Inductors Using CFOAs and Analog Multipliers

New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capacitor) and not requiring any component-matching conditions and design constraints for the intended type of inductance realization. The workability and applications of the new circuits have been demonstrated by SPICE simulation and hardware experimental results based upon AD844-type CFOAs and AD633-type/MPY534 type analog multipliers.

14-bit 100 MS/s 121 mW pipelined ADC

This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18/zm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range （SFDR） and signal-to-noise plus distortion ratio （SNDR） of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.

A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS

A new loading-balanced architecture for high speed and low power consumption pipeline analog-todigital converter（ADC） is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing technique, capacitor-scaling scheme to reduce the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage, by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system＇s point of view, all load capacitors of the shared OTAs are balanced by employing a loadingbalanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of 1.2×1.2 mm^2. The measurement results show a 55.58 dB signal-to-noise-and-distortion ratio（SNDR） and 62.97 dB spurious-free dynamic range（SFDR） with a 25 MHz input operating at a 200 MS/s sampling rate. The proposed ADC consumes 115 m W at 200 MS/s from a 1.8 V supply.

Approaching Quantum-Limited Amplification with Large Gain Catalyzed by Optical Parametric Amplifier Medium

Amplifier is at the heart of experiments carrying out the precise measurement of a weak signal. An idea quantum amplifier should have a large gain and minimum added noise simultaneously. Here, we consider the quantum measurement properties of the cavity with the OPA medium in the op-amp mode to amplify an input signal. We show that our nonlinear-cavity quantum amplifier has large gain in the single-value stable regime and achieves quantum limit unconditionally.

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.

Optimization Design of Two-Stage Operational Amplifier with Frequency Compensation via Geometric Programming

An optimization design technique to obtain global solution for a two-stage operational amplifier(op-amp) with frequency compensation is presented.This frequency compensation technique can adjust the equivalent resistance to guarantee that the phase margin is stable even though circumstance temperature varies.Geometric programming is used to optimize the component values and transistor dimensions.It is used in this analog integrated circuit design to calculate these parameters automatically.This globally optimal amplifier obtains minimum power while other specifications are fulfilled.