ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to ...ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.展开更多
为解决传统数字滤波器在有限精度实现时因有限字长(Finite Word Length,FWL)效应导致滤波器性能下降的问题,提出一种L_(2)灵敏度最小化的数字滤波器状态空间实现稀疏化方法.推导前向差分算子数字滤波器结构传输函数及其等效状态空间实现...为解决传统数字滤波器在有限精度实现时因有限字长(Finite Word Length,FWL)效应导致滤波器性能下降的问题,提出一种L_(2)灵敏度最小化的数字滤波器状态空间实现稀疏化方法.推导前向差分算子数字滤波器结构传输函数及其等效状态空间实现,根据可控及可观格莱姆矩阵得到基于相似变换矩阵的L_(2)灵敏度表达式,并进行稀疏化校准,将L_(2)灵敏度最小化问题转换为凸函数求最值问题,求导得到L_(2)灵敏度最小化表达式,代回即得前向差分算子数字滤波器的稀疏化状态空间实现.仿真结果表明,所提方法设计的数字滤波器具有更好的抗FWL效应.展开更多
The study on designs for the baseline parameterization has aroused attention in recent years. This paper focuses on two-level regular designs for the baseline parameterization. A general result on the relationship bet...The study on designs for the baseline parameterization has aroused attention in recent years. This paper focuses on two-level regular designs for the baseline parameterization. A general result on the relationship between K-aberration and word length pattern is developed.展开更多
文摘ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.
文摘为解决传统数字滤波器在有限精度实现时因有限字长(Finite Word Length,FWL)效应导致滤波器性能下降的问题,提出一种L_(2)灵敏度最小化的数字滤波器状态空间实现稀疏化方法.推导前向差分算子数字滤波器结构传输函数及其等效状态空间实现,根据可控及可观格莱姆矩阵得到基于相似变换矩阵的L_(2)灵敏度表达式,并进行稀疏化校准,将L_(2)灵敏度最小化问题转换为凸函数求最值问题,求导得到L_(2)灵敏度最小化表达式,代回即得前向差分算子数字滤波器的稀疏化状态空间实现.仿真结果表明,所提方法设计的数字滤波器具有更好的抗FWL效应.
文摘The study on designs for the baseline parameterization has aroused attention in recent years. This paper focuses on two-level regular designs for the baseline parameterization. A general result on the relationship between K-aberration and word length pattern is developed.
