With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW...With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW codesign method to implement the H.264 decoder in an SoC with an ARM core, a multimedia processor and a deblocking filter coprocessor. For the parallel processing features of the multimedia processor, clock cycles of decoding process can be dramatically reduced. And the hardware dedicated deblocking filter coprocessor can improve the efficiency a lot. With maximum clock frequency of 150 MHz, the whole system can achieve real time processing speed and flexibility.展开更多
This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design...This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.展开更多
This paper proposes an integrated joint source-channel decoder （I-JSCD） using Max-Log-MAP method for sources encoded with exp-Golomb codes and convolutional codes, and proposes a system applying this method to decod...This paper proposes an integrated joint source-channel decoder （I-JSCD） using Max-Log-MAP method for sources encoded with exp-Golomb codes and convolutional codes, and proposes a system applying this method to decoding the VLC data, e.g. motion vector differences （MVDs）, of H.264 across an AWGN channel. This method combines the source code state-space and the channel code state-space together to construct a joint state-space, develops a 3-D trellis and a maximum a-posterior （MAP） algorithm to estimate the source sequence symbol by symbol, and then uses max-log approximation to simplify the algorithm. Experiments indicate that the proposed system gives significant improvements on peak signal-to-noise ratio （PSNR） （maximum about 15 dB） than a separate scheme. This also leads to a higher visual quality of video stream over a highly noisy channel.展开更多
网络流媒体播放控件能很大程度地减轻程序开发人员的负担,编程人员只需简单地设置控件的属性就可轻松完成视频的实时播放.基于x264解码代码,在Visual Studio 2008平台下,考虑实际网络状况以及代码复杂性等问题,利用双缓冲循环队列、管...网络流媒体播放控件能很大程度地减轻程序开发人员的负担,编程人员只需简单地设置控件的属性就可轻松完成视频的实时播放.基于x264解码代码,在Visual Studio 2008平台下,考虑实际网络状况以及代码复杂性等问题,利用双缓冲循环队列、管道通信等技术,构建了一个完整的H.264流媒体播放路径,整合成一个参数可配置、功能丰富的流媒体播放控件.该控件结构清晰,配置灵活,功能丰富,使用方便.展开更多
文摘With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW codesign method to implement the H.264 decoder in an SoC with an ARM core, a multimedia processor and a deblocking filter coprocessor. For the parallel processing features of the multimedia processor, clock cycles of decoding process can be dramatically reduced. And the hardware dedicated deblocking filter coprocessor can improve the efficiency a lot. With maximum clock frequency of 150 MHz, the whole system can achieve real time processing speed and flexibility.
基金Project supported by the Applied Materials Shanghai Research and Development Foundation (Grant No.08700741000)the Foundation of Shanghai Municipal Education Commission (Grant No.2006AZ068)
文摘This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.
基金Supported by the Foundation of Ministry of Education of China (211CERS10)
文摘This paper proposes an integrated joint source-channel decoder （I-JSCD） using Max-Log-MAP method for sources encoded with exp-Golomb codes and convolutional codes, and proposes a system applying this method to decoding the VLC data, e.g. motion vector differences （MVDs）, of H.264 across an AWGN channel. This method combines the source code state-space and the channel code state-space together to construct a joint state-space, develops a 3-D trellis and a maximum a-posterior （MAP） algorithm to estimate the source sequence symbol by symbol, and then uses max-log approximation to simplify the algorithm. Experiments indicate that the proposed system gives significant improvements on peak signal-to-noise ratio （PSNR） （maximum about 15 dB） than a separate scheme. This also leads to a higher visual quality of video stream over a highly noisy channel.
文摘网络流媒体播放控件能很大程度地减轻程序开发人员的负担,编程人员只需简单地设置控件的属性就可轻松完成视频的实时播放.基于x264解码代码,在Visual Studio 2008平台下,考虑实际网络状况以及代码复杂性等问题,利用双缓冲循环队列、管道通信等技术,构建了一个完整的H.264流媒体播放路径,整合成一个参数可配置、功能丰富的流媒体播放控件.该控件结构清晰,配置灵活,功能丰富,使用方便.
