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Wafer-scale fabrication of carbon-nanotube-based CMOS transistors and circuits with high thermal stability 被引量:1
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作者 Nan Wei Ningfei Gao +7 位作者 Haitao Xu Zhen Liu Lei Gao Haoxin Jiang Yu Tian Yufeng Chen Xiaodong Du Lian-Mao Peng 《Nano Research》 SCIE EI CSCD 2022年第11期9875-9880,共6页
Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication proce... Thanks to its single-atomic-layer structure,high carrier transport,and low power dissipation,carbon nanotube electronics is a leading candidate towards beyond-silicon technologies.Its low temperature fabrication processes enable three-dimensional(3D)integration with logic and memory(static random access memory(SRAM),magnetic random access memory(MRAM),resistive random access memory(RRAM),etc.)to realize efficient near-memory computing.Importantly,carbon nanotube transistors require good thermal stability up to 400℃ processing temperature to be compatible with back-end-of-line(BEOL)process,which has not been previously addressed.In this work,we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity,where AlN was employed as electrostatic doping layer.The gate stack and passivation layer were optimized to realize high-quality interfaces.Specifically,we demonstrate 1-bit carbon nanotube full adders working under 250℃ with rail-to-rail outputs. 展开更多
关键词 carbon nanotube field-effect transistors complementary metal-oxide-semiconductor(CMOS) thermal stability waferscale integrated circuits
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