Boolean process

Boolean algebra successfully describes the logical behavior of a digital circuit, and has been widely used in electronic circuit design and test With the development of high speed VLSIs it is a drawback for Boolean algebra to be unable to describe circuit timing behavior. Therefore a Boolean process is defined as a family of Boolean van ables relevant to the time parameter t. A real-valued sample of a Boolean process is a waveform. Waveform functions can be manipulated formally by using mathematical tools. The distance, difference and limit of a waveform polynomial are defined, and a sufficient and necessary condition of the limit existence is presented. Based on this, the concept of sensitization is redefined precisely to demonstrate the potential and wide application possibility The new definition is very different from the traditional one, and has an impact on determining the sensitizable paths with maximum or minimum length, and false paths, and then designing and testing high performance

Testability Analysis at Switch Level for CMOS Circuits

In this paper we propose a controllability and observability measure at switch level for CMOS circuits based on the cost analysis approach.The complexity of the algorithm is nearly linear.

PROGRAMMABLE LOGIC ARRAYS WITH THE PROPERTIES OF EASY TEST GENERATION

Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design with added product terms and/or outputs such that tests are easy to generate, even no effort on test generation and fault simulation is necessary. This paper attempts to further clarify the concept of ETG circuits and extends the concepts of pseudo-nonconcurrency and separation to reduce the hardware overhead, based on a unified singlefault model. Experimental results show that the hardware overhead is generally less than 5%, which is considered to be the lowest cost for testable PLA designs.

60-GHz array antenna with standard CMOS technology on Schott Borofloat

This design is presented of a 2 × 2 planar array, with a half-wave dipole antenna to be its element, on a new substrate material, Schott Borofloat, with CMOS technology in the 60 GHz band. In the proposed structure, all the designs are based on the CMOS technology and similar performance could be achieved with the same size in contrast to the design on low-temperature co-fired ceramic （LTCC）. This could lead to the improving of the compatibility with the CMOS IC process, the design cost and the design precision which is restricted in the LTCC process. The simulated-10 dB bandwidth of the array is from 58 to 64 GHz. A peak gain of 9.4 dBi is achieved. Good agreement on return loss is achieved between simulations and measurements.

DLJ:A Dynamic Line-Justification Algorithm for Test Generation

Line justification is a basic factor in affecting the efficiency of algorithms for test generation.The existence of reconvergent fanouts in the circuit under test resalts in backtracks in the process of line justification.In order to reduce the number of backtracks and shorten the processing time between backtracks,we present a new algorithm called DLJ(dynamic line justification)in which two techniques are employed.1.A cost function called“FOCOST”is proposed as heuristic information to represent the cost of justifying a certain line.When the relations among the lines being justified are“and”,the line having the highest FOCOST should be chosen.When the relations are“or”,the line having the lowest FOCOST should be chosen.The computing of the FOCOST of lines is very simple.2. Disjoint justification cubes dynamically generated to perform backtracks make the backtrack number of the algorithm minimal.When the backtrace with cube C_1 does not yield a solution,the next cube to be chosen is C′_2=C_2-{C_1,C_2}.Experimental results demonstrate that the combination of the two techniques effectively reduces the backtracks and accelerates the test generation.

Product-Oriented Test-Pattern Generation for Programmable Logic Arrays

A Product-oriented test-pattern generation strategy for Programmable Logic Arrays(PLAs)is pres- ented.First the personality of products is discussed.Products are divided into several categories to speed up the test generation.This strategy aims at generating a very compact test set for crosspoint defects through the fol- lowing steps:1)generate special test vectors for each category of products at the beginning of test generation. Each vector is capable of detecting a great amount of crosspoint defects;2)generate test vectors for the defects which are not covered by the tests already generated.In this step,some heuristics are employed to accelerate test generation.Based on this strategy,a PLA test-pattern generation system is developed and the experimen- tal results are analyzed.

Pseudo-Random Test Generation for Large Combinational Circuits

In this paper,a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing.Several interesting experimental results are obtained.It is found out that initial states of pseudo-random sequences have little effect on fault coverage.Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less than the number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as m decreases.The local unrandomness of pseudo-random sequences is exposed clearly.Generally,when an LFSR is employed as a pseudo-random generator,there are at least as many LFSR stages as circuit inputs.However,for large circuits under test with hundreds of inputs,there are drawbacks of using an LFSR with hundreds of stages.In the paper,a new design for a pseudo-random pattern generator is proposed in which m<n.The relationship between test length and the number of LFSR stages is discussed in order to obtain necessary,fault coverage.It is shown that the design cannot only save LFSR hardware but also reduce test length without loss of fault coverage,and is easy to implement. The experimental results are provided for the 10 Benchmark Circuits to show the effectiveness of the generator.

SABATPG-A Structural Analysis Based Automatic Test Generation System

A TPG system, SABATPG, is given based on a generic structural model of large circuits. Three techniques of partial implication, aftereffect of identified undetectable faults and shared sensitization with new concepts of localization and aftereffect are employed in the system to improve FAN algorithm. Experiments for the 10 ISCAS benchmark circuits show that the computing time of SABATPG for test generation is 19.42% less than that of FAN algorithm.

A Data Manager for Engineering Applications

Efficient data management is crucial to the success of a CAD/CAM system.Traditional database systems,designed to deal with only regular and structural data,cannot efficiently manage design data. In this paper,we present a data manager called EDBMS/2,which has been developed by our laboratory for engineering support applications.EDBMS/2 has a data model that combines features of both relational and semantic ones and owns flexible abilities for modeling engineering data,such as variable-length data processing,integrated management of structured data and unstructured data,and composite object handling.Mechanisms based on DBV and DBV graph concepts,proposed in EDBMS/2,make EDBMS/2 own powerful abilities for version management and run efficiently.By now,EDBMS/2 has been used successfully in EDCADS(integrated Electronic Devices CAD environ- ment)project and as a lower level support to develop an object-oriented DBMS for mechanical engineering.

HEPAPS:A PCB Automatic Placement System

HEPAPS is composed of constructive placement,improving placement,equivalence pins reassignment and same function elements reassignment.Based on practical demands,this paper imple- ments the constructive procedure within a set of engineering constraints and resolves the reassignment problems of equivalence and same function elements.A new topological improving method combined min-cut algorithm with simulated annealing algorithm is presented.In addition,the two-dimensional relaxed method is introduced to solve the geometrical optimization problem.

Test Derivation Through Critical Path Transitions

In this paper,a new technique called test derivation is presented,aiming at the promotion of the random testing efficiency for combinational circuits.Combined with a fault simulator based on critical path tracing method,we introduce the concept of seed test derivation and attempt to generate a group of new tests from the seed test by means of critical path transition.The necessary conditions and effi- cient algorithms are proposed to guarantee the usefulness of the newly derived tests and the correctness of the critical path transitions.Also,examples are given to demonstrate the effectiveness of the technique.

A Domain Knowledge Driven Approach for User Interface Software Development

A domain knowledge driven user interface development approach is described.As a conceptual de- sign of the user interface,the domain knowledge defines the user interface in terms of objects,actions and their relationships that the user would use to interact with the application system.It also serves as input to a user interface management system(UIMS)and is the kernel of the target user interface. The principal ideas and the implementation techniques of the approach is discussed.The user interface model,user interface designer oriented high-level specification notation,and the transformation algorithms on domain knowledge are presented.

Probabilistic Models for Estimation of Random and Pseudo-Random Test Length

A new probabilistic testability measure is presented to ease test length analyses of random testing and pseudorandom testing.The testability measure given in this paper is oriented to signal conflict of reconvergent fanouts.Test length analyses in this paper are based on a hard fault set,calculations of which are practicable and simple.Experimental results have been obtained to show the accuracy of this test length analyser in comparison with that of Savir,Chin and McCluskey,and Wunderlich by using a pseudorandom test generator combined with exhaustive fault simulation.

Deductive Fault Simulation Algorithm Based on Fault Collapsing

The true value simulation is necessary in the critical path tracing fault simulation algorithm.The critical and non-critical inputs can be known after the number of controlling and non-controlling inputs and the criticality of output of every gate are determined.Single output region(SOR)is defined for non-critical lines,so many other non-critical lines can be obtained before fault simulation.Then deductive fault simulation algorithm is used to compute the fault list for every possible critical line from bottom to top,which can greatly decrease the length of fault list and simulation time.The cross-section is defined to reduce the storage space.The experimental results are given at the end of the paper.

Information Model for Product Modeling

The Key problems in product modeling for integrated CAD∥CAM systems are the information structures and representations of products.They are taking more and more important roles in engi- neering applications.With the investigation on engineering product information and from the viewpoint of industrial process,in this paper,the information models are proposed and the definitions of the framework of product information are given.And then,the integration and the consistence of product information are discussed by introducing the entity and its instance.As a summary,the information structures described in this paper have many advantages and natures helpful in engineering design.

An Environment for Rapid Prototyping of Interactive Systems

This paper shows an environment which supports the development of multi-thread dialogue interactive systems.The environment includes several tools and run-time support programs for the design and implementation of the user interface of an interactive system.First,methods of user interface specifica- tion with Elementary Nets are discussed.Then,the syntax of a user interface specification language based on Elementary Nets and the pre-compiler for the language as well as a graphic editor for Elemen- tary Nets construction are described.Finally,an example is given to illustrate the design process of a user interface.

Aliasing Errors in Parallel Signature Analyzers

A Linear Feedback Shift Register (LFSR)can be used to compress test response data as a Signature Analyzer(SA). Parallel Signature Analyzers (PSAs) implemented as multiple input LFSRs are faster and re- quire less hardware overhead than Serial Signature Analyzers (SSAs)for compacting test response data for Built-In Serf-Test (BIST)in IC or hoard-testing environments. However, the SAs are prone to aliasing errors because of some specific types of error patterns. An alias is a faulty output signature that is identical to the fault-free signature. A penetrating analysis of detecting capability of SAs depends strongly on mathematical manipulations, instead of being aware of some special cases or examples. In addition , the analysis should not be restricted to a particular structure of LFSR, but be appropriate for various structures of LFSRs. This pa- per presents necessary and sufficient conditions for aliasing errors based on a complete mathematical descrip- tion of various types of SAs. An LFSR reconfiguration scheme is suggested which will prevent any aliasing double errors. Such a prevention cannot be obtained by any extension of an LFSR.

Discrete Interpolation Surface

In this paper, a method to construct a surface with point interpolation and normal interpolation is presented. An algorithm to construct the discrete interpolation is also presented, which has the time com- plexity O (Nlog N), where N in the number of scattered points.