A novel terminal-optimized triple RESURF LDMOS(TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolarCMOS-DMOS(BCD) process. By introducing a low concentration region to the terminal region, the surface electric f...A novel terminal-optimized triple RESURF LDMOS(TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolarCMOS-DMOS(BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage(BV) and electrostatic discharge(ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse(TLP) tests,direct current(DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance(R_(on,sp)) of 6.99Ω·mm^(2).Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.展开更多
The dependencies of hot-carrier-induced degradations on the effective channel length Lch,eff are investigated for n-type metal-oxide-semiconductor field effect transistor （MOSFETs）. Our experiments find that, with d...The dependencies of hot-carrier-induced degradations on the effective channel length Lch,eff are investigated for n-type metal-oxide-semiconductor field effect transistor （MOSFETs）. Our experiments find that, with decreasing Lch,eff, the saturation drain current （Iasat ） degradation is unexpectedly alleviated. The further study demonstrates that the anomalous Lch,eff dependence of Idsat degradation is induced by the increasing influence of the substrate current degradation on the lazar degradation with Lch,eff reducing.展开更多
This paper proposes a new shallow trench and planar gate MOSFET （TPMOS） structure based on VD- MOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a pl...This paper proposes a new shallow trench and planar gate MOSFET （TPMOS） structure based on VD- MOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only im- proves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.展开更多
基金supported by the National Natural Science Foundation of China (Grant No. 61504049)the China Postdoctoral Science Foundation (Grant No. 2016M600361)the Fundamental Research Funds for the Central Universities,China (Grant No. JUSRP51510)。
文摘A novel terminal-optimized triple RESURF LDMOS(TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolarCMOS-DMOS(BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage(BV) and electrostatic discharge(ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse(TLP) tests,direct current(DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance(R_(on,sp)) of 6.99Ω·mm^(2).Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.
基金Supported by Hong Kong,Macao and Taiwan Science&Technology Cooperation Program of China under Grant No2014DFH10190the Distinguished Young Scientists Foundation of Jiangsu Province under Grant No BK20130021+1 种基金the National Natural Science Foundation of China under Grant Nos 61204083 and 61306092the Qing Lan Project
文摘The dependencies of hot-carrier-induced degradations on the effective channel length Lch,eff are investigated for n-type metal-oxide-semiconductor field effect transistor （MOSFETs）. Our experiments find that, with decreasing Lch,eff, the saturation drain current （Iasat ） degradation is unexpectedly alleviated. The further study demonstrates that the anomalous Lch,eff dependence of Idsat degradation is induced by the increasing influence of the substrate current degradation on the lazar degradation with Lch,eff reducing.
基金Project supported by the Special Science and Technology Plan of Education Bureau of Shaanxi Province,China(No.08JK379)
文摘This paper proposes a new shallow trench and planar gate MOSFET （TPMOS） structure based on VD- MOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only im- proves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.
