Boolean algebra successfully describes the logical behavior of a digital circuit, and has been widely used in electronic circuit design and test With the development of high speed VLSIs it is a drawback for Boolean al...Boolean algebra successfully describes the logical behavior of a digital circuit, and has been widely used in electronic circuit design and test With the development of high speed VLSIs it is a drawback for Boolean algebra to be unable to describe circuit timing behavior. Therefore a Boolean process is defined as a family of Boolean van ables relevant to the time parameter t. A real-valued sample of a Boolean process is a waveform. Waveform functions can be manipulated formally by using mathematical tools. The distance, difference and limit of a waveform polynomial are defined, and a sufficient and necessary condition of the limit existence is presented. Based on this, the concept of sensitization is redefined precisely to demonstrate the potential and wide application possibility The new definition is very different from the traditional one, and has an impact on determining the sensitizable paths with maximum or minimum length, and false paths, and then designing and testing high performance circuits展开更多
Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design wit...Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design with added product terms and/or outputs such that tests are easy to generate, even no effort on test generation and fault simulation is necessary. This paper attempts to further clarify the concept of ETG circuits and extends the concepts of pseudo-nonconcurrency and separation to reduce the hardware overhead, based on a unified singlefault model. Experimental results show that the hardware overhead is generally less than 5%, which is considered to be the lowest cost for testable PLA designs.展开更多
A TPG system, SABATPG, is given based on a generic structural model of large circuits. Three techniques of partial implication, aftereffect of identified undetectable faults and shared sensitization with new concepts ...A TPG system, SABATPG, is given based on a generic structural model of large circuits. Three techniques of partial implication, aftereffect of identified undetectable faults and shared sensitization with new concepts of localization and aftereffect are employed in the system to improve FAN algorithm. Experiments for the 10 ISCAS benchmark circuits show that the computing time of SABATPG for test generation is 19.42% less than that of FAN algorithm.展开更多
The true value simulation is necessary in the critical path tracing fault simulation algorithm.The critical and non-critical inputs can be known after the number of controlling and non-controlling inputs and the criti...The true value simulation is necessary in the critical path tracing fault simulation algorithm.The critical and non-critical inputs can be known after the number of controlling and non-controlling inputs and the criticality of output of every gate are determined.Single output region(SOR)is defined for non-critical lines,so many other non-critical lines can be obtained before fault simulation.Then deductive fault simulation algorithm is used to compute the fault list for every possible critical line from bottom to top,which can greatly decrease the length of fault list and simulation time.The cross-section is defined to reduce the storage space.The experimental results are given at the end of the paper.展开更多
基金Project supported by the National Natural Science Foundation of China.
文摘Boolean algebra successfully describes the logical behavior of a digital circuit, and has been widely used in electronic circuit design and test With the development of high speed VLSIs it is a drawback for Boolean algebra to be unable to describe circuit timing behavior. Therefore a Boolean process is defined as a family of Boolean van ables relevant to the time parameter t. A real-valued sample of a Boolean process is a waveform. Waveform functions can be manipulated formally by using mathematical tools. The distance, difference and limit of a waveform polynomial are defined, and a sufficient and necessary condition of the limit existence is presented. Based on this, the concept of sensitization is redefined precisely to demonstrate the potential and wide application possibility The new definition is very different from the traditional one, and has an impact on determining the sensitizable paths with maximum or minimum length, and false paths, and then designing and testing high performance circuits
基金Project supported by the National Natural Science Foundation of China, and subsidized by K. C. Edu cation Foundation.
文摘Programmable logic array (PLA) is a popular structure for realizing arbitrary combinational networks. Easy test generation (ETG) PLA, a kind of PLA design with the property of easy test generation, is s PLA design with added product terms and/or outputs such that tests are easy to generate, even no effort on test generation and fault simulation is necessary. This paper attempts to further clarify the concept of ETG circuits and extends the concepts of pseudo-nonconcurrency and separation to reduce the hardware overhead, based on a unified singlefault model. Experimental results show that the hardware overhead is generally less than 5%, which is considered to be the lowest cost for testable PLA designs.
文摘A TPG system, SABATPG, is given based on a generic structural model of large circuits. Three techniques of partial implication, aftereffect of identified undetectable faults and shared sensitization with new concepts of localization and aftereffect are employed in the system to improve FAN algorithm. Experiments for the 10 ISCAS benchmark circuits show that the computing time of SABATPG for test generation is 19.42% less than that of FAN algorithm.
文摘The true value simulation is necessary in the critical path tracing fault simulation algorithm.The critical and non-critical inputs can be known after the number of controlling and non-controlling inputs and the criticality of output of every gate are determined.Single output region(SOR)is defined for non-critical lines,so many other non-critical lines can be obtained before fault simulation.Then deductive fault simulation algorithm is used to compute the fault list for every possible critical line from bottom to top,which can greatly decrease the length of fault list and simulation time.The cross-section is defined to reduce the storage space.The experimental results are given at the end of the paper.
