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Optimal impurity distribution model and experimental verification of variation of lateral doping termination
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作者 任敏 叶昶宇 +5 位作者 周建宇 张新 郑芳 马荣耀 李泽宏 张波 《Chinese Physics B》 SCIE EI CAS CSCD 2023年第4期724-729,共6页
Based on the charge balance principle,an optimal impurity distribution variation of lateral doping termination(OIDVLD)and its ion-injection mask design method are proposed and verified.The comparative simulations and ... Based on the charge balance principle,an optimal impurity distribution variation of lateral doping termination(OIDVLD)and its ion-injection mask design method are proposed and verified.The comparative simulations and experiments show that OID-VLD can achieve better blocking ability and reliability than the traditional VLD(T-VLD).Vertical double diffusion MOSFET(VDMOS)with OID-VLD achieved breakdown voltage(BV)of 1684 V and passed the 168 hours 100℃-110℃-120℃-125℃high-temperature reverse bias(HTRB)test,while VDMOS with T-VLD obtained BV of 1636 V and failed in the 20 hours 120℃HTRB test. 展开更多
关键词 variation of lateral doping(VLD) junction termination breakdown voltage RELIABILITY
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Impact of STI indium implantation on reliability of gate oxide
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作者 陈晓亮 陈天 +3 位作者 孙伟锋 钱忠健 李玉岱 金兴成 《Chinese Physics B》 SCIE EI CAS CSCD 2022年第2期671-676,共6页
The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide ... The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap. 展开更多
关键词 SILICON-ON-INSULATOR shallow trench isolation(STI)implantation gate oxide reliability
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Current-Induced Magnetic Switching in an L1_(0) FePt Single Layer with Large Perpendicular Anisotropy Through Spin–Orbit Torque
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作者 Kaifeng Dong Chao Sun +10 位作者 Laizhe Zhu Yiyi Jiao Ying Tao Xin Hu Ruofan Li Shuai Zhang Zhe Guo Shijiang Luo Xiaofei Yang Shaoping Li Long You 《Engineering》 SCIE EI CAS 2022年第5期55-61,共7页
In this study,current-induced partial magnetization-based switching was realized through the spin–orbit torque(SOT)in single-layer L1_(0) FePt with a perpendicular anisotropy(K_(u⊥))of 1.19×10^(7) erg·cm^(... In this study,current-induced partial magnetization-based switching was realized through the spin–orbit torque(SOT)in single-layer L1_(0) FePt with a perpendicular anisotropy(K_(u⊥))of 1.19×10^(7) erg·cm^(-3)(1 erg·cm^(-3)=0.1 J·m^(-3)),and its corresponding SOT efficiency(βDL)was 8×10^(-6) Oe·(A·cm^(-2))^(-1)(1 Oe=79.57747 A·m^(-1)),which is several times higher than that of the traditional Ta/CoFeB/MgO structure reported in past work.The SOT in the FePt films originated from the structural inversion asymmetry in the FePt films since the dislocations and defects were inhomogeneously distributed within the samples.Furthermore,the FePt grown on MgO with a granular structure had a larger effective SOT field and effi-ciency than that grown on SrTiO_(3)(STO)with a continuous structure.The SOT efficiency was found to be considerably dependent on not only the sputtering temperature-induced chemical ordering but also the lattice mismatch-induced evolution of the microstructure.Our findings can provide a useful means of efficiently electrically controlling a magnetic bit that is highly thermally stable via SOT. 展开更多
关键词 L1_(0)FePt SOT Inversion asymmetry Magnetic switching Perpendicular anisotropy
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Micromachined Infrared Thermopile Detector Based on a Suspended Film Structure
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作者 Cheng LEI Yihao GUAN +5 位作者 Ting LIANG Xuezhan WU Yuehang BAI Mingfeng GONG Pingang JIA Jijun XIONG 《Photonic Sensors》 SCIE EI CSCD 2023年第3期50-62,共13页
The micro-electromechanical system(MEMS)infrared thermopile is the core working device of modern information detection systems such as spectrometers,gas sensors,and remote temperature sensors.We presented two differen... The micro-electromechanical system(MEMS)infrared thermopile is the core working device of modern information detection systems such as spectrometers,gas sensors,and remote temperature sensors.We presented two different structures of MEMS infrared thermopiles based on suspended film structures.They both deposited silicon nitride over the entire surface as a passivated absorber layer in place of a separate absorber zone,and the thermocouple strip was oriented in the same direction as the temperature gradient.The same MEMS preparation process was used and finally two different structures of the thermopile were characterized separately for testing to verify the impact of our design on the detector.The test results show that the circular and double-ended symmetrical thermopile detectors have responsivities of 27.932 V/W and 23.205 V/W,specific detectivities of 12.1×10^(7) cm·Hz^(1/2)·W^(-1) and 10.1×10^(7) cm·Hz^(1/2)·W^(-1),and response time of 26.2 ms and 27.06 ms,respectively.In addition,rectangular double-ended symmetric thermopile has a larger field of view than a circular thermopile detector,but is not as mechanically stable as a circular thermopile. 展开更多
关键词 Adiabatic groove circular arrangement double-ended symmetrical arrangement THERMOPILE temperature gradient
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A 0.19 ppm/°C bandgap reference circuit with high-PSRR 被引量:2
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作者 Jing Leng Yangyang Lu +5 位作者 Yunwu Zhang Huan Xu Kongsheng Hu Zhicheng Yu Weifeng Sun Jing Zhu 《Journal of Semiconductors》 EI CAS CSCD 2018年第9期88-94,共7页
A high-order curvature-compensated CMOS bandgap reference(BGR) topology with a low temperature coefficient(TC) over a wide temperature range and a high power supply reject ratio(PSRR) is presented.High-order cor... A high-order curvature-compensated CMOS bandgap reference(BGR) topology with a low temperature coefficient(TC) over a wide temperature range and a high power supply reject ratio(PSRR) is presented.High-order correction is realized by incorporating a nonlinear current INL, which is generated by ?V_(GS) across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of0.19 ppm/°C over the temperature range of 165 °C(-40 to 125 °C), PSRR of-123 d B @ DC and-56 d B @ 100 k Hz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V. 展开更多
关键词 bandgap reference (BGR) temperature coefficient (TC) power supply rejection ratio (PSRR)
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