Pinning consensus analysis of multi-agent networks with arbitrary topology

In this paper the pinning consensus of multi-agent networks with arbitrary topology is investigated. Based on the properties of M-matrix, some criteria of pinning consensus are established for the continuous multi-agent network and the results show that the pinning consensus of the dynamical system depends on the smallest real part of the eigenvalue of the matrix which is composed of the Laplacian matrix of the multi-agent network and the pinning control gains. Meanwhile, the relevant work for the discrete-time system is studied and the corresponding criterion is also obtained. Particularly, the fundamental problem of pinning consensus, that is, what kind of node should be pinned, is investigated and the positive answers to this question are presented. Finally, the correctness of our theoretical findings is demonstrated by some numerical simulated examples.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.