The skin effect in the reversely switched dynistor （RSD） devices is investigated in this paper. Based on the plasma bipolar drift model of the RSD, the current density distributions on the chip are simulated with co...The skin effect in the reversely switched dynistor （RSD） devices is investigated in this paper. Based on the plasma bipolar drift model of the RSD, the current density distributions on the chip are simulated with considering the skin effect. The results indicate that the current density on the border can be several hundred to a thousand A/cm2 higher than that in the center of the chip. The skin effect becomes more prominent as the voltage increases and the inductance decreases in the main circuit. The phenomenon that most of a certain group of chips break over on the border has proved the existence of the skin effect.展开更多
The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor netwo...The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.展开更多
基金supported by the National Natural Science Foundation of China under Grant No.50577028the Specialized Research Fund for the Doctoral Program of Higher Education of China under Grant No.20050487044the China Postdoctoral Science Foundation under Grant No.20080440931
文摘The skin effect in the reversely switched dynistor （RSD） devices is investigated in this paper. Based on the plasma bipolar drift model of the RSD, the current density distributions on the chip are simulated with considering the skin effect. The results indicate that the current density on the border can be several hundred to a thousand A/cm2 higher than that in the center of the chip. The skin effect becomes more prominent as the voltage increases and the inductance decreases in the main circuit. The phenomenon that most of a certain group of chips break over on the border has proved the existence of the skin effect.
基金the Hi-Tech Research and Development Program of China（2006AA01Z226）the Scientific Research Foundation of Huazhong University of Science and Technology（2006Z001B)the Natural Science Foundation of Hubei（2006ABA080）.
文摘The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.
