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Low-complexity systolic architecture for inversion
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作者 袁丹寿 Rong Mengtian 《High Technology Letters》 EI CAS 2006年第4期413-416,共4页
A modified extended binary Euclid' s algorithm which is more regularly iterative for computing an inversion in GF(2^m) is presented. Based on above modified algorithm, a serial-in serial-out architecture is propose... A modified extended binary Euclid' s algorithm which is more regularly iterative for computing an inversion in GF(2^m) is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has area complexity of O(m), latency of 5m - 2, and throughput of 1/m. Compared with other serial systolic arehiteetures, the proposed one has the smallest area complexity, shorter latency. It is highly regular, modular, and thus well suited for high-speed VLSI design. 展开更多
关键词 VLSI INVERSION systolic array Finite field
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