This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and th...This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.展开更多
文摘This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.
