Energy-efficient and security-optimized AES hardware design for ubiquitous computing

Ubiquitous computing must incorporate a certain level of security.For the severely resource con-strained applications,the energy-efficient and small size cryptography algorithm implementation is a critical prob-lem.Hardware implementations of the advanced encryption standard (AES) for authentication and encryption are presented.An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices.It proves that compact AES architectures fail to optimize the AES hardware energy,whereas reducing invalid switching activities and implementing power-optimized sub-modules are the reasonable methods.Implemen-tations of different substitution box (S-Boxes) structures are presented with 0.25 μm 1.8 V CMOS (complementary metal oxide semiconductor) standard cell library.The comparisons and trade-offs among area,security,and power are explored.The experimental results show that Galois field composite S-Boxes have smaller size and highest security but consume considerably more power,whereas decoder-switch-encoder S-Boxes have the best power char-acteristics with disadvantages in terms of size and security.The combination of these two type S-Boxes instead of homogeneous S-Boxes in AES circuit will lead to optimal schemes.The technique of latch-dividing data path is analyzed,and the quantitative simulation results demonstrate that this approach diminishes the glitches effectively at a very low hardware cost.

A band-gap voltage reference for interface circuit of microsensor

A high performance CMOS band-gap voltage reference circuit that can be used in interface integrated circuit of microsensor and compatible with 0. 6 μm ( double poly) mix process is proposed in this paper. The circuit can be employed in the range of 1. 8 - 8 V and carry out the first-order PTAT ( proportional to absolute temperature) temperature compensation. Through using a two-stage op-amp with a NMOS input pair as a negative feedback op-amp,the PSRR ( power supply rejection ratio) of the entire circuit is increased,and the temperature coefficient of reference voltage is decreased. Results from HSPICE simulation show that the PSRR is - 72. 76 dB in the condition of low-frequency,the temperature coefficient is 2. 4 × 10 -6 in the temperature range from - 10 ℃ to 90 ℃ and the power dissipation is only 14 μW when the supply voltage is 1. 8 V.

Simulation and analysis of effects of Young’s modulus of isolation material on natural frequencies of the sensor package and displacement of the chip

For the first time an anti-shock packaging model of an acoustic-vibration sensor system has been designed by using the shocking isolation principle. The finite element analysis has been applied for design and simulation of the model. The effects of Young’s modulus of anti-shock rubber on naturally occurring frequencies of the combination of rubber and an acoustic sensor chip were analyzed. The displacement of the acoustic sensor chip is loaded with force. The results of static analysis and harmonic analysis show that while increasing Young’s modulus of anti-chock rubber, the first five natural frequencies of the package body also increases. Yet the displacement of the acoustic sensor chip around the resonant frequency decreases. The results of static and transient analysis show that the displacement of the acoustic sensor chip decreases with the increase of Young’s modulus of anti-chock rubber being loaded with either transient force or static force at the bottom of the combination of rubber and acoustic sensor chip.

Study of CMOS integrated signal processing circuit in capacitive sensors

A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage’s frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software. Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF～15PF. And the variation of frequency can be easily detected using counter or SCU.