Rietveld refinement of powder X-ray diffraction,microstructural and mechanical studies of magnesium matrix composites processed by high energy ball milling

This research reports the processing of magnesium matrix composites reinforced with silicon carbide(SiC)and aluminium oxide(Al_(2)O_(3))using powder metallurgy technique through high energy milling.Samples of Mg-SiC and Mg-Al_(2)O_(3)composites subjected to high energy ball milling for different vol%of secondary particles 20,30 and 40%of SiC and Al_(2)O_(3)are studied by X-Ray diffraction technique.The rietveld method as implemented in the Fullprof program is applied in order to determine the quantities of the resulting crystalline phases and amorphous phases at each stage of the mechanical treatment.Microstructural examination is carried out using Scanning Electron Microscope(SEM).In addition,crystal structural analysis using appropriate size and strain models is performed in order to handle the distinctive anistrophy that is observed in convinced crystallographic directions for the magnesium composite.The results are furnished in terms of crystalline domains size enlargement of the magnesium composites phases upon prolonged milling duration and discussed in the light of up to date views and theories on crystal growth of nanocrystaline materials.The hardness of the composite samples is calculated by Vickers’s Hardness tester.Further,dry sling wear test and corrosion test are performed for the fabricated composites.Composite with 30%secondary particles incorporated magnesium composites exhibits better wear and corrosion resistance than the other composites.

Efficient Global Threshold Vector Outlyingness Ratio Filter for the Removal of Random Valued Impulse Noise

This research paper proposes a filter to remove Random Valued Impulse Noise (RVIN) based on Global Threshold Vector Outlyingness Ratio (GTVOR) that is applicable for real time image processing. This filter works with the algorithm that breaks the images into various decomposition levels using Discrete Wavelet Transform (DWT) and searches for the noisy pixels using the outlyingness of the pixel. This algorithm has the capability of differentiating high frequency pixels and the “noisy pixel” using the threshold as well as window adjustments. The damage and the loss of information are prevented by means of interior mining. This global threshold based algorithm uses different thresholds for different quadrants of DWT and thus helps in recovery of noisy image even if it is 90% affected. Experimental results exhibit that this method outperforms other existing methods for accurate noise detection and removal, at the same time chain of connectivity is not lost.

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

This paper presents a unique voltage-raising topology for a single-phase seven-level inverter with triple output voltage gain using single input source and two switched capacitors.The output voltage has been boosted up to three times the value of input voltage by configuring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and transformers.The selective harmonic elimination(SHE)approach is used to remove the lower-order harmonics.The optimal switching angles for SHE is determined using the genetic algorithm.These switching angles are com-bined with a level-shifted pulse width modulation(PWM)technique for pulse generation,resulting in reduced total harmonic distortion(THD).A detailed com-parison has been made against other relevant seven-level inverter topologies in terms of the number of switches,drivers,diodes,capacitors,and boosting facil-ities to emphasize the benefits of the proposed model.The proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the results.The Digital Signal Processing(DSP)TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

Artificial Intelligence Based Smart Routing in Software Defined Networks

In a non-static information exchange network,routing is an overly com-plex task to perform,which has to satisfy all the needs of the network.Software Defined Network(SDN)is the latest and widely used technology in the future communication networks,which would provide smart routing that is visible uni-versally.The various features of routing are supported by the information centric network,which minimizes the congestion in the dataflow in a network and pro-vides the content awareness through its mined mastery.Due to the advantages of the information centric network,the concepts of the information-centric net-work has been used in the paper to enable an optimal routing in the software-defined networks.Although there are many advantages in the information-centric network,there are some disadvantages due to the non-static communication prop-erties,which affects the routing in SDN.In this regard,artificial intelligence meth-odology has been used in the proposed approach to solve these difficulties.A detailed analysis has been conducted to map the content awareness with deep learning and deep reinforcement learning with routing.The novel aligned internet investigation technique has been proposed to process the deep reinforcement learning.The performance evaluation of the proposed systems has been con-ducted among various existing approaches and results in optimal load balancing,usage of the bandwidth,and maximization in the throughput of the network.

High Speed and Low Power Architecture for Network Intrusion Detection System

The tremendous growth in the field of modern communication and network systems places demands on the security. As the network complexity grows, the need for the automated detection and timely alert is required to detect the abnormal activities in the network. To diagnose the system against the malicious signatures, a high speed Network Intrusion Detection System is required against the attacks. In the network security applications, Bloom Filters are the key building block. The packets from the high speed link can be easily processed by Bloom Filter using state- of-art hardware based systems. As Bloom Filter and its variant Counting Bloom Filter suffer from False Positive Rate, Multi Hash Counting Bloom Filter architecture is proposed. The proposed work, constitute parallel signature detection improves the False Positive Rate, but the throughput and hardware complexity suffer. To resolve this, a Multi-Level Ranking Scheme is introduced which deduces the 13% - 16% of the power and increases the throughput to 23% - 30%. This work is best suited for signature detection in high speed network.

Cloud Data Encryption and Authentication Based on Enhanced Merkle Hash Tree Method

Many organizations apply cloud computing to store and effectively process data for various applications.The user uploads the data in the cloud has less security due to the unreliable verification process of data integrity.In this research,an enhanced Merkle hash tree method of effective authentication model is proposed in the multi-owner cloud to increase the security of the cloud data.Merkle Hash tree applies the leaf nodes with a hash tag and the non-leaf node contains the table of hash information of child to encrypt the large data.Merkle Hash tree provides the efficient mapping of data and easily identifies the changesmade in the data due to proper structure.The developed model supports privacy-preserving public auditing to provide a secure cloud storage system.The data owners upload the data in the cloud and edit the data using the private key.An enhanced Merkle hash tree method stores the data in the cloud server and splits it into batches.The data files requested by the data owner are audit by a third-party auditor and the multiowner authentication method is applied during the modification process to authenticate the user.The result shows that the proposed method reduces the encryption and decryption time for cloud data storage by 2–167 ms when compared to the existing Advanced Encryption Standard and Blowfish.

Design of Precise Multiplier Using Inexact Compressor for Digital Signal Processing

In the recent years,error recovery circuits in optimized data path units are adopted with approximate computing methodology.In this paper the novel multipliers have effective utilization in the newly proposed two different 4:2 approximate compressors that generate Error free Sum(ES)and Error free Carry(EC).Proposed ES and Proposed EC in 4:2 compressors are used for performing Partial Product(PP)compression.The structural arrangement utilizes Dadda structure based PP.Due to the regularity of PP arrangement Dadda multiplier is chosen for compressor implementation that favors easy standard cell ASIC design.In this,the proposed compression idealogy are more effective in the smallest n columns,and the accurate compressor in the remaining most significant columns.This limits the error in the multiplier output to be not more than 2n for an n X n multiplication.The choice among the proposed compressors is decided based on the significance of the sum and carry signals on the multiplier result.As an enhancement to the proposed multiplier,we introduce two Area Efficient(AE)variants viz.,Proposed-AE(P-AE),and P-AE with Error Recovery(P-AEER).The proposed basic P-AE,and P-AEER designs exhibit 46.7%,52.9%,and 52.7%PDP reduction respectively when compared to an approximate multiplier of minimal error type and are designed with 90nm ASIC technology.The proposed design and their performance validation are done by using Cadence Encounter.The performance evaluations are carried out using cadence encounter with 90nm ASIC technology.The proposed-basic P-AEA and P-AEER designs demonstrate 46.7%,52.9%and 52.7%PDP reduction compared to the minimal error approximate multiplier.The proposed multiplier is implemented in digital image processing which revealed 0.9810 Structural SIMilarity Index(SSIM),to the least,and less than 3%deviation in ECG signal processing application.

Optimization of Thermal Aware VLSI Non-Slicing Floorplanning Using Hybrid Particle Swarm Optimization Algorithm-Harmony Search Algorithm

Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.

Efficient Energy Optimized Faithful Adder with Parallel Carry Generation

Abstract:Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications.This work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry(PC)generation logic.For‘n’bits in input,the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits.A simple OR logic with no carry propagation is used to implement the approximate part.In the exact part,addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical path.Evaluations reveal that the maximum error of the proposed adder confines not more than 2n/2.As an enhancement of the proposed algorithm,we use the Error Recovery(ER)module to reduce the average error.Synthesis results of Proposed-PC(P-PC)and Proposed-PCER(P-PCER)adders with n-16 in 180nm Application Specific Integrated Circuit(ASIC)PDK technology revealed 44.2%&41.7%PDP reductions and 43.4%&40.7%ADP reductions,respectively compared to the latest best approximate design compared.The functional and driving effectiveness of proposed adders are examined through digital image processing applications.