Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macromodeling method applicable to both small-signal and large-signal a...Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macromodeling method applicable to both small-signal and large-signal analysis of general two-stage operational amplifiers （op-amps）. The proposed method creates a two-pole parametric macromodel whose parameters are analytical functions of the circuit element parameters generated by a symbolic circuit simulator. A moment matching technique is used in deriving the analytical model parameter. The created parametric behavioral model can be used for op-amps performance simulation in both frequency and time domains. In particular, the parametric models are highly suited for fast statistical simulation of op-amps in the time-domain. Experiment results show that the statistical distributions of the op-amp slew and settling time characterized by the proposed model agree well with the transistor-level results in addition to achieving significant speedup.展开更多
This paper proposes a multilevel placer targeted at hierarchical FPGA（Field Programmable Gate Array） devices.The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering p...This paper proposes a multilevel placer targeted at hierarchical FPGA（Field Programmable Gate Array） devices.The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement process into a V-cycle.It provides superior wirelength results over a known heuristic high-quality placement tool on a set of large circuits,when restricted to a short run time.For example,it can generate a placement result for a circuit with 5000 4-LUTs（4-Input Look Up Tables） in 70 seconds,almost 30%decrease of wirelength compared with than the heuristic implementation that takes over 500 seconds.We have verified our algorithm yields good quality-time tradeoff results as a low-temperature simulated annealing refinement process can only improve the result by an average of 1.11%at the cost of over 25-fold runtime.展开更多
Crosstalk has become one of the most critical concerns in very deep sub-micron era. This paper deals with the problem of crosstalk mitigation at both methodological and algorithmic levels. Noting that intermediate ope...Crosstalk has become one of the most critical concerns in very deep sub-micron era. This paper deals with the problem of crosstalk mitigation at both methodological and algorithmic levels. Noting that intermediate operations between global routing and detailed routing are very effective in crosstalk estimation and reduction, the authors propose to incorporate several intermediate steps that are separated in traditional design flow into an integrated routing resource assignment stage, so that the operations could easily cooperate to fully exert their power on crosstalk reduction. An efficient priority-based heuristic algorithm is developed, which works slice by slice. Crosstalk avoidance, and ,nany other aspects that are critical in routing practice including congestion, vias, layer preference, etc., are taken into account. A track reservation strategy is adopted in the algorithm framework to compensate the undesired effects caused by sequential routing. Experimental results on a series of ISPD98 and industrial benchmarks show that the proposed approach is able to reduce capacitive crosstalk by about 70% on average without compromising completion ratio compared with a previously reported graph based algorithm, demonstrating the advantages of the approach.展开更多
Deep submicron process technology is widely being used and interconnect structures are becoming more and more complex.This means that the resistance calculation based on two-dimensional models can no longer provide su...Deep submicron process technology is widely being used and interconnect structures are becoming more and more complex.This means that the resistance calculation based on two-dimensional models can no longer provide sufficiently accurate results.This paper presents a three-dimensional resistance calculation method called the combined analytical formula and boundary element method(ABEM).The method cuts selected interconnecting lines then it calculates the resistances of straight sections using an analytical formula and the resistances of the other sections using the boundary element method(BEM).The resistances of the different sub-regions are combined to calculate the resistance of the entire region.Experiments on actual layouts show that compared with the commercial software Raphael based on finite difference method,the proposed method is 2-3 orders of magnitude faster.The ABEM method uses much less memory(about 0.1%-1%),and is more accurate than Raphael with default mesh partitions.The results illustrate that the proposed method is efficient and accurate.展开更多
文摘Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macromodeling method applicable to both small-signal and large-signal analysis of general two-stage operational amplifiers （op-amps）. The proposed method creates a two-pole parametric macromodel whose parameters are analytical functions of the circuit element parameters generated by a symbolic circuit simulator. A moment matching technique is used in deriving the analytical model parameter. The created parametric behavioral model can be used for op-amps performance simulation in both frequency and time domains. In particular, the parametric models are highly suited for fast statistical simulation of op-amps in the time-domain. Experiment results show that the statistical distributions of the op-amp slew and settling time characterized by the proposed model agree well with the transistor-level results in addition to achieving significant speedup.
基金supported by the National Natural Science Foundation of China under Grant Nos.60876026 and 60833004.
文摘This paper proposes a multilevel placer targeted at hierarchical FPGA（Field Programmable Gate Array） devices.The placer is based on multilevel optimization method which combines the multilevel bottom-up clustering process and top-down placement process into a V-cycle.It provides superior wirelength results over a known heuristic high-quality placement tool on a set of large circuits,when restricted to a short run time.For example,it can generate a placement result for a circuit with 5000 4-LUTs（4-Input Look Up Tables） in 70 seconds,almost 30%decrease of wirelength compared with than the heuristic implementation that takes over 500 seconds.We have verified our algorithm yields good quality-time tradeoff results as a low-temperature simulated annealing refinement process can only improve the result by an average of 1.11%at the cost of over 25-fold runtime.
基金This work is supported by the National Hi-Tech Research ＆ Development 863 Program of China under Grant No. 2004AA1Z14600 and the National Natural Science Foundation of China （NSFC） under Grant No, 60476014.
文摘Crosstalk has become one of the most critical concerns in very deep sub-micron era. This paper deals with the problem of crosstalk mitigation at both methodological and algorithmic levels. Noting that intermediate operations between global routing and detailed routing are very effective in crosstalk estimation and reduction, the authors propose to incorporate several intermediate steps that are separated in traditional design flow into an integrated routing resource assignment stage, so that the operations could easily cooperate to fully exert their power on crosstalk reduction. An efficient priority-based heuristic algorithm is developed, which works slice by slice. Crosstalk avoidance, and ,nany other aspects that are critical in routing practice including congestion, vias, layer preference, etc., are taken into account. A track reservation strategy is adopted in the algorithm framework to compensate the undesired effects caused by sequential routing. Experimental results on a series of ISPD98 and industrial benchmarks show that the proposed approach is able to reduce capacitive crosstalk by about 70% on average without compromising completion ratio compared with a previously reported graph based algorithm, demonstrating the advantages of the approach.
基金supported by National Science Foundation of China(No.90407004).
文摘Deep submicron process technology is widely being used and interconnect structures are becoming more and more complex.This means that the resistance calculation based on two-dimensional models can no longer provide sufficiently accurate results.This paper presents a three-dimensional resistance calculation method called the combined analytical formula and boundary element method(ABEM).The method cuts selected interconnecting lines then it calculates the resistances of straight sections using an analytical formula and the resistances of the other sections using the boundary element method(BEM).The resistances of the different sub-regions are combined to calculate the resistance of the entire region.Experiments on actual layouts show that compared with the commercial software Raphael based on finite difference method,the proposed method is 2-3 orders of magnitude faster.The ABEM method uses much less memory(about 0.1%-1%),and is more accurate than Raphael with default mesh partitions.The results illustrate that the proposed method is efficient and accurate.
