以单管Boost型PFC电路作为研究对象,分别针对电流断续、电流临界连续和电流连续3种工作模态,详细讨论了数字控制PFC的实现方法和设计过程,并分别给出了样机实验结果;此外,结合M C 56F 8013的外设资源特点,给出了基于DSP的PFC详细的系统...以单管Boost型PFC电路作为研究对象,分别针对电流断续、电流临界连续和电流连续3种工作模态,详细讨论了数字控制PFC的实现方法和设计过程,并分别给出了样机实验结果;此外,结合M C 56F 8013的外设资源特点,给出了基于DSP的PFC详细的系统接口设计,包括PWM控制策略和同步控制AD采样环节。对PFC的数字控制方案进行了系统研究,提供了不同工作模式下的完整数字控制解决方案,为功率因数的数字控制技术应用提供了较好的参考作用。展开更多
Cooperation between manufacturing and other functional groups is critical to improve the success of new products. However, integrating operations and development methodologies is often challenging due to conflicting p...Cooperation between manufacturing and other functional groups is critical to improve the success of new products. However, integrating operations and development methodologies is often challenging due to conflicting priorities and organizational structures. Improving the quality of product development and the transition to manufacturing is not a new venture. Organizations have been incorporating planning and continuous improvement to their product develop-ment initiatives for decades. This paper summarizes the experience of I/O libraries quality certification within Freescale Semiconductor and describes the certification flow developed by Corporate Quality and I/O Design teams.展开更多
This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of t...This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.展开更多
As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （ESD） failure becomes one of the most devastating IC reliability problems and on-chip ESD protection des...As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （ESD） failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency （RF）, analog, and mixed-signal （AMS） IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.展开更多
文摘以单管Boost型PFC电路作为研究对象,分别针对电流断续、电流临界连续和电流连续3种工作模态,详细讨论了数字控制PFC的实现方法和设计过程,并分别给出了样机实验结果;此外,结合M C 56F 8013的外设资源特点,给出了基于DSP的PFC详细的系统接口设计,包括PWM控制策略和同步控制AD采样环节。对PFC的数字控制方案进行了系统研究,提供了不同工作模式下的完整数字控制解决方案,为功率因数的数字控制技术应用提供了较好的参考作用。
文摘Cooperation between manufacturing and other functional groups is critical to improve the success of new products. However, integrating operations and development methodologies is often challenging due to conflicting priorities and organizational structures. Improving the quality of product development and the transition to manufacturing is not a new venture. Organizations have been incorporating planning and continuous improvement to their product develop-ment initiatives for decades. This paper summarizes the experience of I/O libraries quality certification within Freescale Semiconductor and describes the certification flow developed by Corporate Quality and I/O Design teams.
文摘This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.
文摘As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （ESD） failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency （RF）, analog, and mixed-signal （AMS） IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.
