A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

A CMOS long-term evolution(LTE) direct convert receiver that eliminates the interstage SAW filter is presented.The receiver consists of a low noise variable gain transconductance amplifier(TCA),a quadrature passive current commutating mixer with a 25%duty-cycle LO,a trans-impedance amplifier(TIA),a 7th-order Chebyshev filter and programmable gain amplifiers(PGAs).A wide dynamic gain range is allocated in the RF and analog parts.A current commutating passive mixer with a 25%duty-cycle LO improves gain,noise,and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference.Fabricated in a 0.13μm CMOS process,the receiver chain achieves a 107 dB maximum voltage gain,2.7 dB DSB NF(from PAD port),-11 dBm 11P3,and>+65 dBm UP2 after calibration,96 dB dynamic control range with 1 dB steps,less than 2%error vector magnitude(EVM) from 2.3 to 2.7 GHz.The total receiver(total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

Quad-channel broadband compact multi-antenna GNSS down-converter for high-reliability navigation

A high-reliability broadband high-linearity down-converter for multi-antenna global navigation satellite system(GNSS)receiver is presented in this paper.Based on direction-of-arrival estimation,the multi-antenna GNSS receiver can separate the GNSS signals from the interfering signals and suppress harmful broadband radio frequency interferences.To drive the off-chip 50Ω2 resistive load and meet the stringent requirements of linearity,a quad-channel down-converter with a broadband common-gate low-noise transcon-ductance amplifier,current-driven passive mixer and novel bridge mode transimpedance driving amplifier have been proposed to contruct the multi-antenna recelver.The operating frequency of this down-converter is from 1.15 to 1.65 GHz,covering all bands for global positioning system(GPS),Beidou navigation satellite system(BDS),global navigation satellite system(GLONASS)and Galileo.The measured results show that the proposed quad-channel down-converter achieves+38 dBm output 3rd order intercept point(OIP3)and+17 dBm OP1dB(output-referred 1 dB compression point),9.5 dB to 12.9 dB noise figure(NF)across the variable gain of 10 dB to 27 dB and approximately 47 dB channel isolation.

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

A CMOS RF front-end for the long-term evolution（LTE） direct conversion receiver is presented.With a low noise transconductance amplifier（LNA）,current commutating passive mixer and transimpedance operational amplifier（TIA）,the RF front-end structure enables high-integration,high linearity and simple frequency planning for LTE multi-band applications.Large variable gain is achieved using current-steering transconductance stages.A current commutating passive mixer with 25%duty-cycle LO improves gain,noise and linearity.A direct coupled current-input filter（DCF） is employed to suppress the out-of-band interferer.Fabricated in a 0.13-μm CMOS process,the RF front-end achieves a 45 dB conversion voltage gain,2.7 dB NF,-7 dBm IIP3,and ＋60 dBm IIP2 with calibration from 2.3 to 2.7 GHz.The total RF front end with divider draws 40 mA from a single 1.2-V supply.

A wide-band low phase noise LC-tuned VCO with constant K_(VCO)/ω_(osc) for LTE PLL

A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or Vdd.The switches are controlled by switching bits.With this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.

An RF frontend circuit design of a Compass and GPS dual-mode dual-channel image rejection radio receiver

This paper introduces a fully integrated low power consumption radio receiver frontend circuit for a Compass（Beidou） and GPS dual mode dual channel system with 2.5 dB NF,1.02 mm^2 areas,and 8 mA of current in 0.18μm TSMC CMOS process.Except for a few passive components for input matching,other components such as an off-chip low noise amplifier or a balun are not required.With a non-tunable passive image rejection filter,the receiver frontend can achieve around 60 dB gain and 34 dB image rejection.

An on-chip temperature compensation circuit for an InGaP/GaAs HBT RF power amplifier

A new on-chip temperature compensation circuit for a GaAs-based HBT RF amplifier applied to wireless communication is presented.The simple compensation circuit is composed of one GaAs HBT and five resistors with various values,which allow the power amplifier to achieve better thermal characteristics with a little degradation in performance.It effectively compensates for the temperature variation of the gain and the output power of the power amplifier by regulating the base quiescent bias current.The temperature compensation circuit is applied to a 3-stage integrated power amplifier for wireless communication applications,which results in an improvement in the gain variation from 4.0 to 1.1 dB in the temperature range between -20 and ＋80℃.

A single die 1.2 V 55 to 95 dB DR delta sigma ADC with configurable modulator and OSR

A single die 1.2 V multi-stage noise shaping（Mash） 2-2 delta sigma analog to digital converter（ADC）for wide applications is implemented. The configurable Mash 2-2 modulator with a new decimation filter design is presented to achieve wide and high dynamic range（DR） for multiple practical applications. The novel modulator can be configured as a Mash 2-2 modulator for high precision or a 2-order modulator for low DR. The decimation filter is designed to select the OSR flexibly among cascaded integrator comb（CIC） filter and two half-band filters（HBF）. The serial peripheral interface（SPI） can be used to adjust the sampling frequency and the oversampling ratio（OSR）. The design was fabricated in a 0.13 m CMOS process with an area of 0.91 mm2and a total power of 5.2 mW. The measurement results show that the dynamic range（DR） of the proposed ADC can change from 55to 95 dB with the configurable OSR from 16 to 256. The spurious free dynamic range（SFDR） and signal-to-noise distortion ratio（SNDR） can get 99 dB and 86.5 dB, respectively.