A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

A constant loop bandwidth fractionalN frequency synthesizer for portable civilian global navigation satellite system （GNSS） receivers implemented in a 130 nm 1P6M CMOS process is introduced. Via discrete work ing regions, the LCVCO obtains a wide tuning range with a simple structure and small VCO gain. Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps. The optimized band width is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies. Measurement results show that this synthesizer attains an inband phase noise lower than 93 dBc at a 10 kHz offset and a spur less than 70 dBc; the bandwidth varies by 4 3% for all the GNSS signals. The whole synthesizer consumes 4.5 mA current from a 1 V supply, and its area （without the LO tested buffer） is 0.5 mm2.

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control （AGC） circuit with a novel DC offset cancel- lation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What＇s more, a novel DC offset cancellation （DCOC） circuit with an HPCF （high pass cutoff frequency） less than 10 kHz is proposed. The AGC is fabricated by a 0.18μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 ×300μm2.

An output amplitude configurable wideband automatic gain control with high gain step accuracy

An output amplitude configurable wideband automatic gain control（AGC） with high gain step accuracy for the GNSS receiver is presented.The amplitude of an AGC is configurable in order to cooperate with baseband chips to achieve interference suppression and be compatible with different full range ADCs.And what’s more,the gain-boosting technology is introduced and the circuit is improved to increase the step accuracy.A zero,which is composed by the source feedback resistance and the source capacity,is introduced to compensate for the pole.The AGC is fabricated in a 0.18μm CMOS process.The AGC shows a 62 dB gain control range by 1 dB each step with a gain error of less than 0.2 dB.The AGC provides 3 dB bandwidth larger than 80 MHz and the overall power consumption is less than 1.8 mA,and the die area is 800 x 300μm^2.

A dual-mode complex filter for GNSS receivers with frequency tuning

A fifth/seventh order dual-mode OTA-C complex filter for global navigation satellite system receivers is implemented in a 0.18μm CMOS process.This filter can be configured as the narrow mode of a 4.4 MHz bandwidth center at 4.1 MHz or the wide mode of a 22 MHz bandwidth center at 15.42 MHz.A fully differential OTA with source degeneration is used to provide sufficient linearity.Furthermore,a ring CCO based frequency tuning scheme is proposed to reduce frequency variation.The measured results show that in narrow-band mode the image rejection ratio（IMRR）is 35 dB,the filter dissipates 0.8 mA from the 1.8 V power supply,and the out-of-band rejection is 50 dB at 6 MHz offset.In wide-band mode,IMRR is 28 dB and the filter dissipates 3.2 mA.The frequency tuning error is less than±2%.

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier（VGA） for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning range from 5 to 87 dB when the control voltage varies from 0 to 1.8 V.The 3 dB bandwidth is about 80 MHz for all levels of control voltage（all gains）.Also,the DC offset cancellation circuit can effectively suppress DC offset to a value of less than 40 mV at the output regardless of the input.The overall power consumption is less than 3 mA,and die area is 705×100μm^2.

A novel 2.95–3.65 GHz CMOS LC-VCO using tuning curve compensation

This paper presents a new CMOS LC-VCO with a 2.95–3.65 GHz tuning range.The large tuning range is achieved by tuning curve compensation using a novel varactor configuration,which is mainly composed of four accumulation-mode MOS varactors（A-MOS）and two bias voltages.The proposed varactor has the advantages of optimizing quality factor and tuning range simultaneously,linearizing the effective capacitance and thus greatly reducing the amplitude-to-phase modulation（AM-PM）conversion.The circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS process.Measured phase noise is lower than–91 dBc at 100 kHz offset from a 3.15 GHz carrier while measured tuning range is 21.5%as the control voltage varies from 0 to 1.8 V.The VCO including buffers consumes 2.8 mA current from a 1.8 V supply.

A reconfigurable OTA-C baseband filter with wide digital tuning for GNSS receivers

The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μm RFCMOS process is proposed.The filter can be configured as a complex band pass filter or two real low pass filters.An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations.An extended tuning range（above 8：1） is obtained by using widely continuously tunable transconductors based on digital techniques.In the complex band pass mode,the bandwidth can be tuned from 3 to 24 MHz and the center frequency from 3 to 16 MHz.

A low-phase-noise LC-VCO with an enhanced-Q varactor for use in a high-sensitivity GNSS receiver

An LC-VCO with an enhanced quality factor（Q） varactor for use in a high-sensitivity GNSS receiver is presented.An enhanced A-MOS varactor is composed of two accumulation-mode MOS（A-MOS） varactors and two bias voltages,which show the improved Q and linearization capacitance-voltage（C-V） curve.The VCO gain（K_（vco）） is compensated by a digital switched varactors array（DSVA） over entire sub-bands.Based on the characteristics of an A-MOS,the varactor in a DSVA is a high Q fixed capacitor as it is switched off,and a moderate Q tuning varactor when it is switched on,which keeps the maximal Q for the LC-tank.The proposed circuit is fabricated in a 0.18μm 1P6M CMOS process.The measured phase noise is better than -122 dBc/Hz at a 1 MHz offset while the measured tuning range is 58.2%and the variation of K_（VCO） is close to±21%over the whole of the sub-bands and the effective range of the control voltage.The proposed VCO dissipates less than 5.4 mW over the whole operating range from a 1.8 V supply.

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured ttming range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

A high linearity SiGe HBT LNA for GPS receiver

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.

A single-to-differential low-noise amplifier with low differential output imbalance

This paper presents a single-ended input differential output low-noise amplifier intended for GPS applications. We propose a method to reduce the gain/amplitude and phase imbalance of a differential output exploiting the inductive coupling of a transformer or center-tapped differential inductor.A detailed analysis of the theory of imbalance reduction,as well as a discussion on the principle of choosing the dimensions of a transformer,are given.An LNA has been implemented using TSMC 0.18μm technology with ESD-protected.Measurement on board shows a voltage gain of 24.6 dB at 1.575 GHz and a noise figure of 3.2 dB.The gain imbalance is below 0.2 dB and phase imbalance is less than 2 degrees.The LNA consumes 5.2 mA from a 1.8 V supply.

A sub-1-dB noise figure monolithic GNSS LNA

A monolithic integrated low noise amplifier （LNA） based on a SiGe H/3T process tbr a global nawgatlon satellite system （GNSS） is presented. An optimizing strategy of taking parasitic capacities at the input node into consideration is adopted and a method and design equations of monolithically designing the LC load and the output impedance matching circuit are introduced. The LNA simultaneously reaches excellent noise and input/output impedance matching. The measurement results show that the LNA gives an ultra-low noise figure of 0.97 dB, a power gain of 18.6 dB and a three-order input intermodulation point of -6 dBm at the frequency of 1.575 GHz. The chip consumes 5.4 mW from a 1.8 V source and occupies 600 x 650 μmz die area.

A low-power CMOS frequency synthesizer for GPS receivers

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18μm CMOS process is introduced.By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time,the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased,compared with traditional prescalers.Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset,with spurs less than-65 dBc.The whole synthesizer consumes 6 mA in the case of a 1.8 V supply,and its core area is 0.6 mm;.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

An inductorless multi-mode RF front end for a global navigation satellite system （GNSS） receiver is presented. Unlike the traditional topology of a low noise amplifier （LNA）, the inductorless current-mode noise- canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier （RFA） further am- plifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down- converts the signals to the intermediate frequency （IF） band and conveys the signals to the analogue blocks. The local oscillator （LO） buffer divides the output frequency of the voltage controlled oscillator （VCO） and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220×280 μm2.

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented. The power solution involves a DC-DC buck converter and a followed low-dropout regulator （LDO）. The pulsewidth-modulation （PWM） control method is adopted for better noise performance. An improved low-power highfrequency PWM control circuit is proposed, which halves the average quiescent current of the buck converter to 80 μA by periodically shutting down the OTA. The size of the output stage has also been optimized to achieve high efficiency under a light load condition. In addition, a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current. Fabricated with commercial 180-nm CMOS technology, the DC-DC converter achieves a peak efficiency of 93.1% under a 2 MHz working frequency. The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.