Effects of oxygen/nitrogen co-incorporation on regulation of growth and properties of boron-doped diamond films

Regulation with nitrogen and oxygen co-doping on growth and properties of boron doped diamond films is studied by using laughing gas as dopant. As the concentration of laughing gas(N2O/C) increases from 0 to 10%, the growth rate of diamond film decreases gradually, and the nitrogen-vacancy(NV) center luminescence intensity increases first and then weakens. The results show that oxygen in laughing gas has a strong inhibitory effect on formation of NV centers, and the inhibitory effect would be stronger as the concentration of laughing gas increases. As a result, the film growth rate and nitrogen-related compensation donor decrease, beneficial to increase the acceptor concentration(~3.2×10^(19)cm^(-3)) in the film. Moreover, it is found that the optimal regulation with the quality and electrical properties of boron doped diamond films could be realized by adding appropriate laughing gas, especially the hole mobility(~700cm^(2)/V·s), which is beneficial to the realization of high-quality boron doped diamond films and high-level optoelectronic device applications in the future.

Temperature-insensitive reading of a flash memory cell

The temperature characteristics of the read current of the NOR embedded flash memory with a 1.5T-per-cell structure are theoretically analyzed and experimentally verified.We verify that for a cell programmed with a“10”state,the read current is either increasing,decreasing,or invariable with the temperature,essentially depending on the reading overdrive voltage of the selected bitcell,or its programming strength.By precisely controlling the programming strength and thus manipulating its temperature coefficient,we propose a new setting method for the reference cells that programs each of reference cells to a charge state with a temperature coefficient closely tracking tail data cells,thereby solving the current coefficient mismatch and improving the read window.

Contact etch process optimization for RF process wafer edge yield improvement

Radio-frequency(RF)process products suffer from a wafer edge low yield issue,which is induced by contact opening.A failure mechanism has been proposed that is based on the characteristics of a wafer edge film stack.The large step height at the wafer's edge leads to worse planarization for the sparse poly-pattern region during the inter-layer dielectric(ILD)chemical mechanical polishing(CMP)process.A thicker bottom anti-reflect coating(BARC)layer was introduced for a sparse poly-pattern at the wafer edge region.The contact open issue was solved by increasing the break through(BT)time to get a large enough window.Well profile and resistance uniformity were obtained by contact etch recipe optimization.

Effect of oxygen on regulation of properties of moderately boron-doped diamond films

Regulation of oxygen on properties of moderately boron-doped diamond films is fully investigated.Results show that,with adding a small amount of oxygen(oxygen-to-carbon ratio<5.0%),the crystal quality of diamond is improved,and a suppression effect of residual nitrogen is observed.With increasing ratio of O/C from 2.5%to 20.0%,the hole concentration is firstly increased then reduced.This change of hole concentration is also explained.Moreover,the results of Hall effect measurement with temperatures from 300 K to 825 K show that,with adding a small amount of oxygen,boron and oxygen complex structures(especially B_(3)O and B_(4)O)are formed and exhibit as shallow donor in diamond,which results in increase of donor concentration.With further increase of ratio of O/C,the inhibitory behaviors of oxygen on boron leads to decrease of acceptor concentration(the optical emission spectroscopy has shown that it is decreased with ratio of O/C more than 10.0%).This work demonstrates that oxygen-doping induced increasement of the crystalline and surface quality could be restored by the co-doping with oxygen.The technique could achieve boron-doped diamond films with both high quality and acceptable hole concentration,which is applicable to electronic level of usage.

Research on COB De-embedding in Scattering Parameter Measurement

The popular radio frequency(RF) chip on board(COB) test has gradually taken the place of onwafer test due to the high efficiency and high power. This paper presents the extended Open-Short-Load(OSL) that is one-port calibration method to verify the error model de-embedding in S parameter measurement. Threelevel cascade structure on COB's system error model is proposed and analyzed. Four kinds of calibration plane solutions for de-embedding are verified. At last,on-board calibration(CAL) kits solution is established to decrease the system error to the least value. The maximum error shift can be controlled less than 0.1 dB comparing with the on-wafer test results. In general,the practical application results prove that this method is reasonable and effective and easy to be mastered.

Design of high reliability RF-LDMOS by suppressing the parasitic bipolar effect using enhanced p-well and double epitaxy

A laterally diffused metal-oxide-semiconductor （LDMOS） device design with an enhanced p-well and double p-epitaxial structure is investigated for device ruggedness improvement while keeping its high device per- formance under high frequency. Based upon the device design, radio-frequency （RF） LDMOS transistors for GSM （global system for mobile communication） application have been fabricated by using 0.35/zm CMOS technolo- gies. Experimental data show that the proposed device achieves a breakdown voltage of 70 V, output power of 180 W. The RF linear gain is over 20 dB and the power added efficiency （PAE） is over 70% with the frequency of 920 MHz. In particular, it can pass the 20 ： 1 voltage standing wave ratio （VSWR） load mismatch biased at drain DC supply voltage of 32 V and output power at 10-dB gain compression point （P10dB）. The device ruggedness has been remarkably improved by using the proposed device structure.

An effective approach to improve split-gate flash product data retention

Data retention is one of the most important reliability characteristics of split-gate flash.Therefore,many efforts were made to improve data retention of split-gate flash.By experiments,it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data retention.Thus,reducing chlorine concentration is an effective approach to improve data retention for split-gate flash product.Additional RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration,and improve FGSP2 oxide film quality,and then get better data retention.

A novel symmetrical split-gate structure for 2-bit per cell flash memory

A fully self-aligned symmetrical split-gate cell structure for 2-bit per cell flash memory with a very competitive bit size is presented. One common select gate is located between two floating gates and a pair of source/drain junctions are shared by the 2 bits. The fabrication method utilized here to create a self-aligned structure is to form a spacer against the prior layer without any additional mask. Although the cell consists of three channels in a series, the attributes from conventional split gate flash are still preserved with appropriate bias conditions. Program and erase operation is performed by using a source side injection （SSI） and a poly-to-poly tunneling mechanism respectively.

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.