Optimized operation scheme of flash-memory-based neural network online training with ultra-high endurance

With the rapid development of machine learning,the demand for high-efficient computing becomes more and more urgent.To break the bottleneck of the traditional Von Neumann architecture,computing-in-memory(CIM)has attracted increasing attention in recent years.In this work,to provide a feasible CIM solution for the large-scale neural networks(NN)requiring continuous weight updating in online training,a flash-based computing-in-memory with high endurance(10^(9) cycles)and ultrafast programming speed is investigated.On the one hand,the proposed programming scheme of channel hot electron injection(CHEI)and hot hole injection(HHI)demonstrate high linearity,symmetric potentiation,and a depression process,which help to improve the training speed and accuracy.On the other hand,the low-damage programming scheme and memory window(MW)optimizations can suppress cell degradation effectively with improved computing accuracy.Even after 109 cycles,the leakage current(I_(off))of cells remains sub-10pA,ensuring the large-scale computing ability of memory.Further characterizations are done on read disturb to demonstrate its robust reliabilities.By processing CIFAR-10 tasks,it is evident that~90%accuracy can be achieved after 109 cycles in both ResNet50 and VGG16 NN.Our results suggest that flash-based CIM has great potential to overcome the limitations of traditional Von Neumann architectures and enable high-performance NN online training,which pave the way for further development of artificial intelligence(AI)accelerators.

Progress of power field effect transistor based on ultra-wide bandgap Ga_2O_3 semiconductor material

As a promising ultra-wide bandgap semiconductor, gallium oxide(Ga_2O_3) has attracted increasing attention in recent years. The high theoretical breakdown electrical field(8 MV/cm), ultra-wide bandgap(～ 4.8 eV) and large Baliga's figure of merit(BFOM) of Ga_2O_3 make it a potential candidate material for next generation high-power electronics, including diode and field effect transistor(FET). In this paper, we introduce the basic physical properties of Ga_2O_3 single crystal, and review the recent research process of Ga_2O_3 based field effect transistors. Furthermore, various structures of FETs have been summarized and compared, and the potential of Ga_2O_3 is preliminary revealed. Finally, the prospect of the Ga_2O_3 based FET for power electronics application is analyzed.

Thermal effect on endurance performance of 3-dimensional RRAM crossbar array

Three-dimensional（3D） crossbar array architecture is one of the leading candidates for future ultra-high density nonvolatile memory applications. To realize the technological potential, understanding the reliability mechanisms of the3 D RRAM array has become a field of intense research. In this work, the endurance performance of the 3D 1D1 R crossbar array under the thermal effect is investigated in terms of numerical simulation. It is revealed that the endurance performance of the 3D 1D1 R array would be seriously deteriorated under thermal effects as the feature size scales down to a relatively small value. A possible method to alleviate the thermal effects is provided and verified by numerical simulation.

Total dose radiation response of modified commercial silicon-on-insulator materials with nitrogen implanted buried oxide

Nitrogen ions of various doses are implanted into the buried oxide （BOX） of commercial silicon-on-insulator （SOI） materials, and subsequent annealings are carried out at various temperatures. The total dose radiation responses of the nitrogen-implanted SOI wafers are characterized by the high frequency capacitance-voltage （C-V） technique after irradi- ation using a Co-60 source. It is found that there exist relatively complex relationships between the radiation hardness of the nitrogen implanted BOX and the nitrogen implantation dose at different irradiation doses. The experimental results also suggest that a lower dose nitrogen implantation and a higher post-implantation annealing temperature are suitable for improving the radiation hardness of SOI wafer. Based on the measured C V data, secondary ion mass spectrometry （SIMS）, and Fourier transform infrared （FTIR） spectroscopy, the total dose responses of the nitrogen-implanted SOI wafers are discussed.

Energy distribution extraction of negative charges responsible for positive bias temperature instability

A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.

SERS devices with "hedgehog-like" nanosphere arrays for detection of trace pesticides

The development of surface-enhanced Raman scattering(SERS)devices for detection of trace pesticides has attracted more and more attention.In this work,a large-area self-assembly ap-proach assisted with reactive ion etching(RIE)is proposed for preparing SERS devices consisting of Ag-covered"hedgehog-like"nanosphere arrays(Ag/HLNAs).Such a SERS device has an enhancement factor of 2.79×107,a limit of detection(LOD)up to 10-12 M for Rhodamine 6G(R6G)analytes,and a relative standard deviation(RSD)smaller than 10%,demonstrating high uniformity.Besides,for pesticide detections,the device achieves an LOD of 10-s M for thiram molecules.It indicates that the proposed SERS device has a promising opportunity in detecting toxic organic pesticides.

A survey of high-speed high-resolution current steering DACs

Digital to analog converters(DAC)play an important role as a bridge connecting the analog world and the digital world.With the rapid development of wireless communication,wideband digital radar,and other emerging technologies,better performing high-speed high-resolution DACs are required.In those applications,signal bandwidth and high-frequency linearity often limited by data converters are the bottleneck of the system.This article reviews the state-of-the-art technologies of high-speed and high-resolution DACs reported in recent years.Comparisons are made between different architectures,circuit implementations and calibration techniques along with the figure of merit(FoM)results.

The n-type Si-based materials applied on the front surface of IBC-SHJ solar cells

Interdigitated back contact silicon hetero-junction(IBC-SHJ) solar cells exhibit excellent performance owing to the IBC and SHJ structures.The front surface field(FSF) layer composed of electric field passivation and chemical passivation has been proved to play an important role in IBC-SHJ solar cells.The electric field passivated layer n^+-a-Si: H, an n-type Si alloy with carbon or oxygen in amorphous phase, is simulated in this study to investigate its effect on IBC-SHJ.It is indicated that the n^+-a-Si: H layer with wider band gap can reduce the light absorption on the front side efficaciously,which hinders the surface recombination of photo-generated carriers and thus contributes to the improvement of the short circuit current density Jsc.The highly doped n^+-a-Si: H can result in the remakable energy band bending, which makes it outstanding in the field passivation, while it makes little contribution to the chemical passivation.It is noteworthy that when the electric field intensity exceeds 1.3 × 10^5 V/cm, the efficiency decrease caused by the inferior chemical passivation is only 0.16%.In this study, the IBC-SHJ solar cell with a front n^+-a-Si: H field passivation layer is simulated, which shows the high efficiency of 26% in spite of the inferior chemical passivation on the front surface.

Multi-Dimensional Models of SiC Power MOSFET for Accurately Predicting the Characteristics

The paper presents a compact simulation program with integrated circuit emphasis(SPICE)model for a 1200V/19A Silicon Carbide power metallic oxide semiconductor field effect transistor(MOSFET).Based on an equivalent circuit topology,the model completely describes the static and dynamic device characteristics which include the MOSFET channel current,the nonlinear junction capacitance and the switching behavior.Especially the parasitic elements effect is also considered and studied during the modeling,testing and simulation.The model parameters are extracted based on the experimental measurement data.For convenience,the model is implemented by Verilog-A description language and embedded in the simulation software-Advanced Design System(ADS).The validity and accuracy of the model are validated by the double pulse test under inductor load.The Verification result shows that the modeling job is correct and available for prediction of the switching performance under different conditions.

Texture engineering of mono-crystalline silicon via alcohol-free alkali solution for efficient PERC solar cells

Control of texture structures is an effective method to reduce surface reflectivity and enhance the efficiency of solar cells.In this paper,pyramid structures are prepared on mono-crystalline silicon wafers by cyclodextrin as surfactant to slow down the etching rate in alcohol-free alkali solution.Compared with volatile alcohol surfactant(e.g.isopropanol,IPA),the cyclodextrin not only possesses a relative high boiling point(1534.4℃),but displays non-toxic and biodegradable properties.Furthermore,the surface morphology,average reflectivity,surface recombination of mono-crystalline silicon wafers were studied in detail.The results show that cyclodextrin can decrease the size and depth of pyramid structures,and thus a lower average reflectivity of 7.5%was obtained.In addition,ray tracing simulation was performed to calculate the photo-generated carrier concentration of PN junction with different sizes of pyramids,and the conclusion is that the carrier concentration of small pyramids is much higher than that of large pyramids.Finally,the average efficiency of large-area mono-crystalline silicon PERC solar cells fabricated by cyclodextrin surfactant was 22.69%,which was 0.43%absolutely higher than that of conventional IPA surfactant.

The physical process analysis of the capacitance-voltage characteristics of AlGaN/AlN/GaN high electron mobility transistors

This paper deduces the expression of the Schottky contact capacitance of AlGaN/A1N/GaN high electron mobility transistors （HEMTs）, which will help to understand the electron depleting process. Some material parameters related with capacitance-voltage profiling are given in the expression. Detailed analysis of the forward-biased capacitance has been carried on. The gate capacitance of undoped AlGaN/AlN/GaN HEMT will fall under forward bias. If a rising profile is obviously observed, the donor-like impurity or trap is possibly introduced in the barrier.

Study on the dose rate upset effect of partially depleted silicon-on-insulator static random access memory

This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM （Partially Depleted Silicon- On-Insulator Static Random Access Memory） with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM （Static Random Access Memory） chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about l×10s Gy（Si）/s. However, there are a few bits upset when the dose rate reaches up to 1.58 x 109 Gy（Si）/s. The SRAM circuit can still work after the high level 3~ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.

An integrated split and dummy gates MOSFET with fast turn-off and reverse recovery characteristics

A power MOSFET with integrated split gate and dummy gate(SD-MOS) is proposed and demonstrated by the TCAD SENTAURUS.The split gate is surrounded by the source and shielded by the dummy gate.Consequently,the coupling area between the split gate and the drain electrode is reduced,thus the gate-to-drain charge(Q_(GD)),reverse transfer capacitance(C_(RSS)) and turn-off loss(E_(off)) are significantly decreased.Moreover,the MOS-channel diode is controlled by the dummy gate with ultra-thin gate oxide t_(ox),which can be turned on before the parasitic P-base/N-drift diode at the reverse conduction,then the majority carriers are injected to the N-drift to attenuate the minority injection.Therefore,the reverse recovery charge(Q_(RR)),time(T_(RR)) and peak current(I_(RRM)) are effectively reduced at the reverse freewheeling state.Additionally,the specific on-resistance(R_(on,sp)) and breakdown voltage(BV) are also studied to evaluate the static properties of the proposed SD-MOS.The simulation results show that the Q_(GD) of 6 nC/cm^(2),the C_(RSS) of 1.1 pF/cm^(2) at the V_(DS) of 150 V,the QRR of 1.2 μC/cm^(2) and the R_(on,sp) of 8.4 mΩ·cm^(2) are obtained,thus the figures of merit(FOM) including Q_(GD) ×R_(on,sp) of50 nC·mΩ,E_(off) × R_(on,sp) of 0.59 mJ·mΩ and the Q_(RR) × R_(on,sp) of 10.1 μC·mΩ are achieved for the proposed SD-MOS.

Low-cost dual-stage offset-cancelled sense amplifier with hybrid read reference generator for improved read performance of RRAM at advanced technology nodes

In this work,two process-variation-tolerant schemes for a current-mode sense amplifier(CSA)of RRAM were proposed:(1)hybrid read reference generator(HRRG)that tracks process-voltage-temperature(PVT)variations and solve the nonlinear issue of the RRAM cells;(2)a two-stage offset-cancelled current sense amplifier(TSOCC-SA)with only two capacitors achieves a double sensing margin and a high tolerance of device mismatch.The simulation results in 28 nm CMOS technology show that the HRRG can provide a read reference that tracks PVT variations and solves the nonlinear issue of the RRAM cells.The proposed TSOCC-SA can tolerate over 64% device mismatch.

Investigation on the passivation,band alignment,gate charge,and mobility degradation of the Ge MOSFET with a GeO/Al;O;gate stack by ozone oxidation

Ge has been an alternative channel material for the performance enhancement of complementary metal-oxide-semiconductor(CMOS)technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology.The gate structure plays a key role on the electrical property.In this paper,the property of Ge MOSFET with Al_(2)O_(3)/GeO_(x)/Ge stack by ozone oxidation is reviewed.The GeO_(x)passivation mechanism by ozone oxidation and band align-ment of Al2O3/GeO_(x)/Ge stack is described.In addition,the charge distribution in the gate stack and remote Coulomb scatter-ing on carrier mobility is also presented.The surface passivation is mainly attributed to the high oxidation state of Ge.The en-ergy band alignment is well explained by the gap state theory.The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility.These investigations help to provide an impressive un-derstanding and a possible instructive method to improve the performance of Ge devices.

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.

Raman and infrared spectra of complex low energy tetrahedral carbon allotropes from first-principles calculations

Up to now,at least 806 carbon allotropes have been proposed theoretically.Three interesting carbon allotropes(named Pbam-32,P6/mmm,and I43d)were recently uncovered based on a random sampling strategy combined with space group and graph theory.The calculation results show that they are superhard and remarkably stable compared with previously proposed metastable phases.This indicates that they are likely to be synthesized in experiment.We use the factor group analysis method to analyze theirΓ-point vibrational modes.Owing to their large number of atoms in primitive unit cells(32 atoms in Pbam-32,36 atoms in P6/mmm,and 94 atoms in I43d),they have many Raman-and infrared-active modes.There are 48 Raman-active modes and 37 infrared-active modes in Pbam-32,24 Raman-active modes and 14 infrared-active modes in P6/mmm,and 34 Raman-active modes and 35 Raman-and infrared-active modes in I43d.Their calculated Raman spectra can be divided into middle frequency range from 600 cm-1 to 1150 cm-1 and high frequency range above 1150 cm-1.Their largest infrared intensities are 0.82,0.77,and 0.70(D/Å)2/amu for Pbam,P6/mmm,and I43d,respectively.Our calculated results provide an insight into the lattice vibrational spectra of these sp3 carbon allotropes and suggest that the middle frequency Raman shift and infrared spectrum may play a key role in identifying newly proposed carbon allotropes.

Transmission through array of subwavelength metallic slits curved with a single step or mutli-step

The transmission of normally incident plane wave through an array of subwavelength metallic slits curved with a sin- gle step or mutli-step has been explored theoretically. The transmission spectrum is simulated by using the finite-difference time-domain method. The influences of surface plasmon polaritons make the end of finite long sub-wavelength metallic slit behaves as magnetic-reflecting barrier. The electromagnetic fields in the subwavelength metallic slits are the superpo- sition of standing wave and traveling wave. The standing electromagnetic oscillation behaves like LC oscillating circuit to decide the resonance wavelength. Therefore, the parameters of adding step may change the LC circuit and influence the transmission wavelength. A new explanation model is proposed in which the resonant wavelength is decided by four factors： the changed length for electric field, the changed length for magnetic field, the effective coefficient of capacitance, and the effective coefficient of inductance. The effect of adding step is presented to analyze the interaction of two steps in slit with mutli-step. This explanation model has been proved by the transmission through arrayed subwavelength metallic slits curved with two steps and fractal steps. All calculated results are well explained by our proposed model.

Development and Prospect of Process Models and Simulation Methods for Atomic Layer Deposition

Thin film deposition is one of the most important processes in IC manufacturing. In this paper, several typical models and numerical simulation methods for thin film deposition and atomic layer deposition are introduced. Several modeling methods based on the characteristics of atomic layer deposition are introduced, it includes geometric method, cellular automata and multiscale simulation. The principle of each model and simulation method is explained, and their advantages and disadvantages are analyzed. Finally, the development direction of thin film deposition and atomic layer deposition modeling is prospected, and some modeling ideas are also provided.

Recognition and Visualization of Lithography Defects based on Transfer Learning

Yield control in the integrated circuit manufacturing process is very important,and defects are one of the main factors affecting chip yield.As the process control becomes more and more critical and the critical dimension becomes smaller and smaller,the identification and location of defects is particularly important.This paper uses a machine learning algorithm based on transfer learning and two fine-tuned neural network models to realize the autonomous recognition and classification of defects even the data set is small,which achieves 94.6%and 91.7%classification accuracy.The influence of network complexity on classification result is studied at the same time.This paper also establishes a visual display algorithm of defects,shows the process of extracting the deep-level features of the defective image by the network,and then analyze the defect features.Finally,the Gradient-weighted Class Activation Mapping technology is used to generate defect heat maps,which locate the defect positions and probability intensity effects.This paper greatly expands the application of transfer learning in the field of integrated circuit lithography defect recognition,and greatly improves the friendliness of defect display.