A single-ended wideband reconfigurable receiver front-end for multi-mode multi-standard applications in 0.18μm CMOS

This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.

A tunable passive mixer for SAW-less front-end with reconfigurable voltage conversion gain and intermediate frequency bandwidth

An adjustable mixer for surface acoustic wave( SAW)-less radio frequency( RF) front-end is presented in this paper. Through changing the bias voltage,the presented mixer with reconfigurable voltage conversion gain( VCG) is suitable for multi-mode multi-standard( MMMS) applications. An equivalent local oscillator( LO) frequency-tunable high-Q band-pass filter( BPF) at low noise amplifier( LNA) output is used to reject the out-of-band interference signals. Base-band( BB) capacitor of the mixer is variable to obtain 15 kinds of intermediate frequency( IF) bandwidth( BW). The proposed passive mixer with LNA is implemented in TSMC 0. 18μm RF CMOS process and operates from 0. 5 to 2. 5 GHz with measured maximum out-of-band rejection larger than 40 d B. The measured VCG of the front-end can be changed from 5 to 17 d B; the maximum input intercept point( IIP3) is0 d Bm and the minimum noise figure( NF) is 3. 7 d B. The chip occupies an area of 0. 44 mm^2 including pads.

Modeling and nonlinear analysis of 14 bit 100MS/s pipelined ADC

In this paper,detailed models of 14-bit 100 MS/s pipelined analog-to-digital converter( ADC)are presented. In order to help design of ADC system,blocks for pipelined ADC and disturbance sources are carefully analyzed. Critical parameters,such as capacitor mismatch,clock jitter are proposed and simulated. The pipelined ADC system is divided into five parts,clock generator,sample and hold( S/H) circuit,multiplying digital-to-analog converters( MDAC),backend,and digital correction. These blocks introduce several interferences,which attenuate performance of pipelined ADC severely. Modeling and simulations of these disturbance sources are presented particularly. A new model of S/H is introduced. Results derived from simulations can supervise design and optimization of the ADC system.

A novel method of optimizing latch comparators

A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematical model to optimize latch design. A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time. In order to suppress offset of latch, the cross-coupled loading, adopted in telescope preamplifier, which enhances the gain, is well analyzed and designed. The chip is fabricated in 0.18 μm CMOS technology. The delay time of latch comparator is less than 400 ps @500 MHz. The offset of comparator is estimated through Monte Carlo simulation. And power consumption is only 144 W under 1.8 V power supply. Results of on wafer testing are presented at the end of the paper. The chip occupies an area of 0.66×0.55 mm^2 and drains current of 80 μA.