Microelectronic neural bridging of toad nerves to restore leg function

The present study used a microelectronic neural bridge comprised of electrode arrays for neural signal detection, functional electrical stimulation, and a microelectronic circuit including signal amplifying, processing, and functional electrical stimulation to bridge two separate nerves, and to restore the lost function of one nerve. The left leg of one spinal toad was subjected to external mechanical stimulation and functional electrical stimulation driving. The function of the left leg of one spinal toad was regenerated to the corresponding leg of another spinal toad using a microelectronic neural bridge. Oscilloscope tracings showed that the electromyographic signals from controlled spinal toads were generated by neural signals that controlled the spinal toad, and there was a delay between signals. This study demonstrates that microelectronic neural bridging can be used to restore neural function between different injured nerves.

Effect of DFE error propagation and its mitigation using MUX-based FEC interleaving for 400 GbE electrical link

This paper evaluates the effect of decision feedback equalizer( DFE) error propagation for400 Gb/s Ethernet( 400 GbE) electrical link in order to propose some effective methods to improve bit error rate( BER). First,an analytical model for DFE burst error length distribution is proposed and simulated based on a NRZ electrical link in which a 5-tap DFE combined with a multiple-tap feed forward equalizer( FFE) is included. Then,a detailed derivation for BER considering DFE error propagation is given based on the distribution of burst error run length and the BER performance with and without forward error correction( FEC) is simulated too. After that,this paper investigates several MUX-based FEC interleaving methods including their complexity and latency in order to improve BER further. At last,three FEC interleaving schemes are compared not only in interleaving gain,but also in hardware complexities and latencies. Simulation results show that pre-interleave bit muxing can obtain good tradeoff between BER and complexity for 400 Gb E electrical link.

A 10Gb/s combined equalizer in 0.18μm CMOS technology for backplane communication

This paper presents a 10Gb/s high-speed equalizer as the front-end of a receiver for backplane communication.The equalizer combines an analog equalizer and a two-tap decision-feedback equalizer in a half-rate structure to reduce the inter-symbol-interference(ISI) of the communication channel.By employing inductive peaking technique for the high-frequency boost circuit,the bandwidth and the boost of the analog equalizer are improved.The decision-feedback equalizer optimizes the size of the CML-based circuit such as D flip-flops(DFF) and multiplex(MUX),shortening the feedback path delay and speeding up the operation considerably.Designed in the 0.18μm CMOS technology,the equalizer delivers 10Gb/s data over 18-in FR4 trace with 28-dB loss while drawing27-mW from a 1.8-V supply.The overall chip area including pads is 0.6×0.7mm^2.

A low power quadrature up-conversion mixer for WSN application

This paper presents an up-conversion mixer for 2.4GHz wireless sensor networks in 0.18μm RF complementary metal-oxide semiconductor(CMOS)technology.It is based on a double-balanced Gilbert cell type.With two Gilbert cells it was applied quadrature modulation.Operational amplifiers are used in this design to improve the conversion gain under low power consumption.The mixer design is based on 0.18μm RF CMOS process.And the mixer test results indicate that under 1.8V power supply,with input frequency 2.4-2.4835GHz,the conversion voltage gain is 1.2-2dB.When the output frequency is 2.4GHz,its power gain is-4.46dB,and its input referred 1 dB compression point is-11.5dBm and it consumes 1.77mA current.

A 0.35μm CMOS 6.1GHz 1∶4 Static Frequency Divider

A 1∶4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1∶2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better performances. Measurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1∶2 divider consumes 11mW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and other high-speed systems.

Design of high speed LVDS transceiver ICs

The design of low-power LVDS（low voltage differential signaling） transceiver ICs is presented.The LVDS transmitter integrates a common-mode feedback control on chip,while a specially designed pre-charge circuit is proposed to improve the speed of the circuit,making the highest data rate up to 622 Mb/s.For the LVDS receiver design, the performance degradation issues are solved when handling the large input common mode voltages of the conventional LVDS receivers.In addition,the LVDS receiver also supports the failsafe function.The transceiver chips were verified with the CSMC 0.5-μm CMOS process.The measured results showed that,for the LVDS transmitter with the pre-charge technique proposed,the maximum data rate is higher than 622 Mb/s.The power consumption is 6 mA with a 5-V power supply.The LVDS receiver can work properly with a larger input common mode voltage（0.1-2.4 V） but a differential input voltage as low as 100 mV The power consumption is only 1.2 mA with a 5-V supply at the highest data rate of 400 Mb/s.The chip set meets the TIA/EIA-644-A standards and shows its potential prospects in LVDS transmission systems.

A 3.125-Gb/s inductorless transimpedance amplifier for optical communication in 0.35μm CMOS

A 3.125-Gb/s transimpedance amplifier（TIA） for an optical communication system is realized in 0.35μm CMOS technology.The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point.In addition,noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩand -3 dB bandwidth of 2.31 GHz.The measured average input referred noise current spectral density is about 18.8 pA/（？）.The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS.Under a single 3.3-V supply voltage,the TIA consumes only 58.08 mW,including 20 mW from the output buffer.The whole die area is 465×435μm^2.

A wideband low power low phase noise dual-modulus prescaler

This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18μm CMOS process of SMIC. The measured results show that the DMP＇s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 x 30 #m2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier（LNA） with electrostatic discharge protection is proposed.It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given.Based on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 dBm.The DC current is 4 mA under a supply of 1.8 V.

Characterization of on-chip balun with patterned floating shield in 65 nm CMOS

A simple method of balun synthesis is proposed to estimate the balun structure in the operating frequency band.Then,a careful optimization is implemented to evaluate the estimated structure by a series of EM simulations. In order to investigate the impact of the patterned floating shield（PFS）,the optimized baluns with and without PFS are fabricated in a 65 nm 1P6M CMOS process.The measurement results demonstrate that the PFS obviously improves the insertion loss（IL） in the frequency range and a linear improving trend appears smoothly.It is also found that the PFS gradually improves the phase balance as the frequency increases,while it has a very slight influence on the magnitude balance.To characterize the device＇s intrinsic power transfer ability,we propose a method to obtain the baluns＇ maximum available gain directly from the measured 3-port S-parameters and find that IL-comparison may not be very objective when evaluating the shielding effect.We also use the resistive coupling efficiency to characterize the shielding effect,and an imbalanced shielding efficiency is found though the PFS is perfectly symmetric in the measurement.It can be demonstrated that this phenomenon comes from the intrinsic imbalance of our balun layout.

A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier（LNA）,a broadband active balun,a high linearity mixer and a bandgap reference（BGR） circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched capacitor at the output port,the LNA can work at two different frequency bands（1.2 GHz and 1.5 GHz） under low power consumption.The active balun uses a hybrid-connection structure to achieve high bandwidth.The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances.The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB,a gain of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz.The power consumption is about 16 mW under a 1.8 V power supply.

A CMOS G_m-C complex filter with on-chip automatic tuning for wireless sensor network application

A Gm-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage.

Design of a 40-GHz LNA in 0.13-μm SiGe BiCMOS

A low-noise amplifier （LNA） operated at 40 GHz is designed. An improved cascode configuration is proposed and the design of matching networks is presented. Short-circuited coplanar waveguides （CPWs） were used as inductors to achieve a high Q-factor. The circuit was fabricated in a 0.13-μm SiGe BiCMOS technology with a transistor transit frequency fT of 103 GHz. The chip area is 0.21mm^2. The LNA has one cascode stage with a-3 dB bandwidth from 34 to 44 GHz. At 40 GHz, the measured gain is 8.6dB; the input return loss, S11, is -16.2dB; and the simulated noise figure is 5 dB. The circuit draws a current of only 3 mA from a 2.5 V supply.

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

A low-jitter RF phase locked loop（PLL） frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with ＇OR＇ logic for dual-modulus operation,the delays associated with both the ＇OR＇ and D-flip-flop（DFF） operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.

Microelectronic neural bridge for signal regeneration and function rebuilding over two separate nerves

According to the feature of neural signals,a micro-electronic neural bridge（MENB）has been designed. It consists of two electrode arrays for neural signal detection and functional electrical stimulation（FES）,and a microelectronic circuit for signal amplifying,processing,and FES driving.The core of the system is realized in 0.5-μm CMOS technology and used in animal experiments.A special experimental strategy has been designed to demonstrate the feasibility of the system.With the help of the MENB,the withdrawal reflex function of the left/right leg of one spinal toad has been rebuilt in the corresponding leg of another spinal toad.According to the coherence analysis between the source and regenerated neural signals,the controlled spinal toad＇s sciatic nerve signal is delayed by 0.72 ms in relation to the sciatic nerve signal of the source spinal toad and the cross-correlation function reaches a value of 0.73.This shows that the regenerated signal is correlated with the source sciatic signal significantly and the neural activities involved in reflex function have been regenerated.The experiment demonstrates that the MENB is useful in rebuilding the neural function between nerves of different bodies.

LC voltage controlled oscillator in 0.18-μm RF CMOS

An integrated low-phase-noise voltage-controlled oscillator （VCO） has been designed and fabricated in SMIC 0.18 μm RF CMOS technology. The circuit employs an optimally designed LC resonator and a differential cross-coupling amplifier acts as a negative resistor to compensate the energy loss of the resonator. To extend the frequency tuning range, a three-bit binary-weighted switched capacitor array is used in the circuit. The testing result indicates that the VCO achieves a tuning range of 60% from 1.92 to 3.35 GHz. The phase noise of the VCO is -117.8 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz. It draws 5.6 mA current from a 1.8 V supply. The VCO integrated circuit occupies a die area of 600 × 900 μm^2. It can be used in the IEEE802.1 lb based wireless local network receiver.

A 50 MHz-1 GHz high linearity CATV amplifier with a 0.15μm InGaAs PHEMT process

A 50 MHz-1 GHz low noise and high linearity amplifier monolithic-microwave integrated-circuit （MMIC） for cable TV is presented.A shunt AC voltage negative feedback combined with source current negative feedback is adopted to extend the bandwidth and linearity.A novel DC bias feedback is introduced to stabilize the operation point,which improved the linearity further.The circuit was fabricated with a 0.15μm InGaAs PHEMT （pseudomorphic high electron mobility transistor） process.The test was carried out in 75Ωsystems from 50 MHz to 1 GHz.The measurement results showed that it gave a small signal gain of 16.5 dB with little gain ripples of less than±1dB.An excellent noise figure of 1.7-2.9 dB is obtained in the designed band.The IIP3 is 16 dBm, which shows very good linearity.The CSO and CTB are high up to 68 dBc and 77 dBc,respectively.The chip area is 0.56 mm^2 and the power dissipation is 110 mA with a 5 V supply.It is ideally suited to cable TV systems.

A CMOS variable gain low-noise amplifier with ESD protection for 5 GHz applications

This paper presents a variable gain low-noise amplifier（VG-LNA） for 5 GHz applications.The effect of the input parasitic capacitance on the inductively degenerated common source LNA＇s input impedance is analyzed in detail.A new ESD and LNA co-design method was proposed to achieve good performance.In addition,by using a simple feedback loop at the second stage of the LNA,continuous gain control is realized.The measurement results of the proposed VG-LNA exhibit 25 dB（-3.3 dB to 21.7 dB） variable gain range,2.8 dB noise figure at the maximum gain and 1 dBm IIP3 at the minimum gain,while the DC power consumption is 9.9 mW under a 1.8 V supply voltage.

A 2.5-Gb/s fully-integrated,low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery （CDR） circuit has been designed and fabricated in SMIC＇s 0.18-μm CMOS technology. The Pottbiicker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of-111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.

A low power 20 GHz comparator in 90 nm COMS technology

A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic （SCL） topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second （GSps） with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.