A 6.25 Gbps SerDes core used in the high speed backplane communication receiver has been designedbased on the OIF-CEI-02.0 standard. To counteract the serious Inter-Symbol-Interference (ISI),the core employed a half-r...A 6.25 Gbps SerDes core used in the high speed backplane communication receiver has been designedbased on the OIF-CEI-02.0 standard. To counteract the serious Inter-Symbol-Interference (ISI),the core employed a half-rate four-tap decision feedback equalizer (DFE). The equalizer used the Sign-signleast mean-squared (SS-LMS) algorithm to realize the coefficient adaptation. An automatic gain control(AGC) amplifier with the sign least mean-squared (S-LMS) algorithm has been used to compensatethe transmission media loss. To recover the clock signal from the input data serial and provide for theDFE and AGC, a bang-bang clock recovery (BB-CR) is adopted. A third order phase loop lock (PLL)model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioralmodeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver.The DFE recovered data over a 34' FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontaleye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.展开更多
基金Supported by the High Technology Research and Development Programme of China (No. 2003AA31g030).
文摘A 6.25 Gbps SerDes core used in the high speed backplane communication receiver has been designedbased on the OIF-CEI-02.0 standard. To counteract the serious Inter-Symbol-Interference (ISI),the core employed a half-rate four-tap decision feedback equalizer (DFE). The equalizer used the Sign-signleast mean-squared (SS-LMS) algorithm to realize the coefficient adaptation. An automatic gain control(AGC) amplifier with the sign least mean-squared (S-LMS) algorithm has been used to compensatethe transmission media loss. To recover the clock signal from the input data serial and provide for theDFE and AGC, a bang-bang clock recovery (BB-CR) is adopted. A third order phase loop lock (PLL)model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioralmodeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver.The DFE recovered data over a 34' FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontaleye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.
