Design of Anti-Collision Integrated Security Mechanism Based on Chaotic Sequence in UHF RFID System

Collision and security issues are considered as barriers to RFID applications.In this paper,a parallelizable anti-collision based on chaotic sequence combined dynamic frame slotted aloha to build a high-efficiency RFID system is proposed.In the tags parallelizable identification,we design a Discrete Markov process to analyze the success identification rate.Then a mutual authentication security protocol merging chaotic anti-collision is presented.The theoretical analysis and simulation results show that the proposed identification scheme has less than 45.1%of the identification time slots compared with the OVSF-system when the length of the chaos sequence is 31.The success identification rate of the proposed chaotic anti-collision can achieve 63%when the number of the tag is100.We test the energy consumption of the presented authentication protocol,which can simultaneously solve the anti-collision and security of the UHF RFID system.

Investigation on the automatic parameters extraction of pulse signals based on wavelet transform

This paper analyses a key problem in the quantification of pulse diagnosis. Due to the subjectivity and fuzziness of pulse diagnosis,quantitative methods are needed. To extract the parameters of pulse signals,the prerequisite is to detect the corners of pulse signals correctly. Up to now,the pulse parameters are mostly acquired by marking the pulse corners manually,which is an obstacle to modernize pulse diagnosis. Therefore,a new automatic parameters extraction approach for pulse signals using wavelet transform is presented. The results testified that the method we proposed is feasible and effective and can detect corners of pulse signals accurately,which can be expected to facilitate the modernization of pulse diagnosis.

Analysis of wave propagation on human body based on stratified media model

Human body communication(HBC) is a promising near-field communication(NFC) method emerging in recent years. But existing theoretical models of HBC are too simple to simulate the wave propagation on human body. In this work, in order to clarify the propagation mechanism of electromagnetic wave on human body, a surface waveguide HBC theoretical model based on stratified media cylinder is presented. A numerical model analyzed by finite element method(FEM) is used for comparing and validating the theoretical model. Finally, results of theoretical and numerical models from 80 MHz to 200 MHz agree fairly well, which means that theoretical model can characterize accurate propagation mechanism of HBC signal. Meanwhile, attenuation constants derived from two kinds of models are within the range from 1.64 to 3.37, so that HBC signal can propagate effectively on human body. The propagation mechanism derived from the theoretical model is useful to provide design information for the transmitter and the modeling of the propagation channel in HBC.

A model for automatic identification of human pulse signals

This paper presents a quantitative method for automatic identification of human pulse signals. The idea is to start with the extraction of characteristic parameters and then to construct the recognition model based on Bayesian networks. To identify depth, frequency and rhythm, several parameters are proposed. To distinguish the strength and shape, which cannot be represented by one or several parameters and are hard to recognize, the main time-domain feature parameters are computed based on the feature points of the pulse signal. Then the extracted parameters are taken as the input and five models for automatic pulse signal identification are constructed based on Bayesian networks. Experimental results demonstrate that the method is feasible and effective in recognizing depth, frequency, rhythm, strength and shape of pulse signals, which can be expected to facilitate the modernization of pulse diagnosis.

Multi-mode controller IC for soft-switched flyback converter with high efficiency over the entire load range

This paper presents a multi-mode control scheme for a soft-switched flyback converter to achieve high efficiency and excellent load regulation over the entire load range. At heavy load, critical conduction mode with valley switching (CCMVS) is employed to realize soft switching so as to reduce turn-on loss of power switch as well as conducted electromagnetic interference (EMI). At light load, the converter operates in discontinuous conduction mode (DCM) with valley switching and adaptive off-time control (AOT) to limit the switching frequency range and maintain load regulation. At extremely light load or in standby mode, burst mode operation is adopted to provide low power consumption through reducing both switching frequency and static power dissipation of the controller. The multi-mode control is implemented by an oscillator whose pulse duration is adjusted by output feedback. An accurate valley switching control circuit guarantees the minimum turn-on voltage drop of power switch. The pro-totype of the controller IC was fabricated in a 1.5-μm BiCMOS process and applied to a 310 V/20 V, 90 W flyback DC/DC converter circuitry. Experimental results showed that all expected functions were realized successfully. The flyback converter achieved a high efficiency of over 80% from full load down to 2.5 W, with the maximum reaching 88.8%, while the total power consumption in standby mode was about 300 mW.

RESEARCH OF FAST MODULAR MULTIPLIER FOR A CLASS OF FINITE FIELDS

A new structure of bit-parallel Polynomial Basis(PB)multiplier is proposed,which isbased on a fast modular reduction method.The method was recommended by the National Instituteof Standards and Technology(NIST).It takes advantage of the characteristics of irreducible polyno-mial,i.e.,the degree of the second item of irreducible polynomial is far less than the degree of thepolynomial in the finite fields GF(2m).Deductions are made for a class of finite field in which trino-mials are chosen as irreducible polynomials.Let the trinomial bex m +x k+1,where 1 ≤k≤?m/2?.??The proposed structure has shorter critical path than the best known one up to date,whilethe space requirement keeps the same.The structure is practical,especially in real time crypto-graphic applications.

A semi-custom design methodology for design performance optimization

We present a semi-custom design methodology based on transistor tuning to optimize the design performance. Compared with other transistor tuning approaches, our tuning process takes the cross-talk effect into account and prominently reduces the complexity for circuit simulation and analysis by decomposing the circuit network utilizing graph theory. Furthermore, the incremental placement and routing for the corresponding transistor tuning in conventional approaches is not required in our methodology, which might induce timing graph variation and additional iterations for design convergence. This methodology combines the flexible automated circuit tuning and physical design tools to provide more opportunities for design optimization throughout the design cycle.

Study of Modeling for Scalable and Monitorable Network on Chip

The performance of multiple processor based on Network on Chip (NoC) is limited to the communication efficiency of network. It is difficult to be optimized of routing and arbitration algorithm and be assessed of performance in the beginning of design because of its complex test cases. This paper constructs a scalable and monitored system level model with SystemC for NoC with Packet Connected Circuit (PCC) protocol. The overall performance and transfer details can be evaluated particularly by running the model, and the statistical basis can also be provided to the optimization of designing NoC.

Artificial Intelligence in Healthcare:Review and Prediction Case Studies

Artificial intelligence(AI)has been developing rapidly in recent years in terms of software algorithms,hardware implementation,and applications in a vast number of areas.In this review,we summarize the latest developments of applications of AI in biomedicine,including disease diagnostics,living assistance,biomedical information processing,and biomedical research.The aim of this review is to keep track of new scientific accomplishments,to understand the availability of technologies,to appreciate the tremendous potential of AI in biomedicine,and to provide researchers in related fields with inspiration.It can be asserted that,just like AI itself,the application of AI in biomedicine is still in its early stage.New progress and breakthroughs will continue to push the frontier and widen the scope of AI application,and fast developments are envisioned in the near future.Two case studies are provided to illustrate the prediction of epileptic seizure occurrences and the filling of a dysfunctional urinary bladder.

The most robust design for digital logics of multiple variables based on neurons with complex-valued weights

Neurons with complex-valued weights have stronger capability because of their multi-valued threshold logic. Neurons with such features may be suitable for solution of different kinds of problems including associative memory,image recognition and digital logical mapping. In this paper,robustness or tolerance is introduced and newly defined for this kind of neuron ac-cording to both their mathematical model and the perceptron neuron's definition of robustness. Also,the most robust design for basic digital logics of multiple variables is proposed based on these robust neurons. Our proof procedure shows that,in robust design each weight only takes the value of i or -i,while the value of threshold is with respect to the number of variables. The results demonstrate the validity and simplicity of using robust neurons for realizing arbitrary digital logical functions.

A NOVEL PHYSICAL-LAYER TRANSCEIVER USED IN USB2.0 SERIAL DATA LINK

The paper proposes a novel transceiver in physical layer for high-speed serial data link based upon Universal Serial Bus (USB) 2.0, comprising transmitter and receiver. In the design, transmitter contains pre-and-main driver to satisfy slew rate of output data, receiver includes optimized topology to improve preci- sion of received data. The circuit simulation is based on Cadence’s spectre software and Taiwan Semiconduc- tor Manufacture Corporation’s library of 0.25μm mixed-signal Complementary Metal-Oxide Semiconductor (CMOS) model. The front and post-simulation results reveal that the transceiver designed can transmit and re- ceive high-speed data in 480Mbps, which is in agreement with USB2.0 specification. The chip of physi- cal-layer transceiver has been designed and implemented with 0.25μm standard CMOS technology.

Design and implementation of a high dimming ratio LED drive controller

This paper presents a high dimming ratio light emitting diode （LED） drive controller chip with digital mode dimming （DMD）. The chip is composed of a boost power converter and a dimming control block. A novel constant on time （COT） control strategy is proposed for boost converter to achieve high dimming ratio. In addition, a fast enough load transient response of the converter power stage ensures its high dimming ratio. The COT control circuit operates mainly based on two current-capacitor timers and a finite state machine （FSM）. The LED drive controller chip is designed and fabricated in 1.5μm bipolar CMOS-DMOS （BCD） process with a die area of 1.31 x 1.43 mm^2. Experimental results show that the proposed LED drive system works well. And, as expected, the minimum LED dimming on time of 1.0μs and the corresponding dimming ratio of 1000 ： 1 at 1 kHz dimming frequency are successfully achieved.

A parallel memory architecture for video coding

To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.

A NEW APPROACH TO PROGRAMMABLE LOGIC ARRAY FOR SINGLE-CLOCK CMOS

Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.

A new DFM flow for sub-100nm standard cells

DFM （Design-For-Manufacturability） method, which aims to improve manufacturability of ICs through specific design considerations, is becoming important nowadays. In particular, standard cells now should be designed by DFM method. This paper reports a new DFM flow for sub-100 nm standard cell design with a group of technologies for process modeling, manufacturability simulation and trial RETs. Based on this flow, a set of DFM-friendly 90nm standard cells were designed.

Modeling of current mismatch induced by random dopant fluctuation in nano-MOSFETs

Deviation of threshold voltage and effective mobility due to random dopant fluctuation is proposed.An improved 65 nm average drain current MOS model calledαlaw is utilized after fitting HSPICE simulating data and extracting process parameters.Then,a current mismatch model of nanoscale MOSFETs induced by random dopant fluctuation is presented based on propagation of variation theory.In test conditions,the calculated standard deviation applying this model,compared to 100 times Monte-Carlo simulation data with HSPICE,indicates that the average relative error and relative standard deviation is 0.24%and 0.22%,respectively.The results show that this mismatch model is effective to illustrate the physical mechanism,as well as being simple and accurate.

Efficient implementation of a cubic-convolution based image scaling engine

In video applications, real-time image scaling techniques are often required. In this paper, an efficient implementation of a scaling engine based on 4×4 cubic convolution is proposed. The cubic convolution has a better performance than other traditional interpolation kernels and can also be realized on hardware. The engine is designed to perform arbitrary scaling ratios with an image resolution smaller than 2560× 1920 pixels and can scale up or down, in horizontal or vertical direction. It is composed of four fimctional units and five line buffers, which makes it more competitive than conventional architectures. A strict fixed-point strategy is applied to minimize the quantization errors of hardware realization. Experimental results show that the engine provides a better image quality and a comparatively lower hardware cost than reference implementations.

Profiling and annotation combined method for multimedia application specific MPSoC performance estimation

Accurate and fast performance estimation is necessary to drive design space exploration and thus support important design decisions. Current techniques are either time consuming or not accurate enough. In this paper, we solve these problems by presenting a hybrid method for multimedia multiprocessor system-on-chip （MPSoC） performance estimation. A general coverage analysis tool GNU gcov is employed to profile the execution statistics during the native simulation. To tackle the complexity and keep the analysis and simulation manageable, the orthogonalization of communication and computation parts is adopted. The estimation result of the computation part is annotated to a transaction accurate model for further analysis, by which a gradual refinement of MPSoC performance estimation is supported. The implementation and its experimental results prove the feasibility and efficiency of the proposed method.

Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation

The application-specific multiprocessor system-on-chip(MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications,which require both high performance and flexible programmability. As an effective method for MPSoC development,we present a gradual refinement flow starting from a high-level Simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels:Simulink combined algorithm and architecture model(CAAM),virtual architecture(VA),transactional accurate architecture(TA),virtual prototype(VP) and field-programmable gate array(FPGA) emulation. Experimental results of Motion-JPEG and H.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original Simulink model,allowing processor,communication and tasks design space exploration.

Third harmonic distortion calculation of a self-oscillating power amplifier

It is difficult to analyze the harmonic distortion of a self-oscillating power amplifier (SOPA),because the SOPA is a hard nonlinear system without an external clock.The single or multiple sinusoidal inputs describing function (DF) method is commonly used to linearize a nonlinear element,but this method considers only the components at the same frequencies as the input signals (i.e.,fundamental components) at the nonlinear element's output.In this paper,besides the fundamental components,the third harmonic components are also calculated at the output of a comparator with three sinusoidal inputs,to create a linearized model of the comparator,and thus of the SOPA.The third harmonic distortion of the SOPA is calculated.The models of the zeroth and the first order SOPA are verified by behavioral simulation using MATLAB.