Parallel-pipelined Architecture of H.264 Deblocking Filter with Adaptive Dynamic Power

In H.264,the computational complexity and memory access of deblocking filter are variable and depend on the video contents. In this paper,a pipelined VLSI architecture of deblocking filter with adaptive dynamic power is proposed. It avoids redundant computations and memory access by precluding the blocks which can be skipped. And the vertical and horizontal edges are simultaneously processed in an advanced scan order to speed up the decoder. As a result,the dynamic power of the proposed architecture can be reduced (up to about 89%) adaptively for different videos. And the off-chip memory access is improved compared to the previous designs. Moreover,the processing capability of the proposed architecture is very appropriate for real-time deblocking of high-definition television (HDTV,1920× 1080 pixel/frame,30 frame/s video signals) video operation at 38 MHz,which significantly outperforms the previous designs from 1.25 times to 4.8 times.

A low drift curvature-compensated bandgap reference with trimming resistive circuit

A low temperature drift curvature-compensated complementary metal oxide semiconductor (CMOS) bandgap ref-erence is proposed.A dual-differential-pair amplifier was employed to add compensation with a high-order term of TlnT (T is the thermodynamic temperature) to the traditional 1st-order compensated bandgap.To reduce the offset of the amplifier and noise of the bandgap reference,input differential metal oxide semiconductor field-effect transistors (MOSFETs) of large size were used in the amplifier and to keep a low quiescent current,these MOSFETs all work in weak inversion.The voltage reference's temperature curvature has been further corrected by trimming a switched resistor network.The circuit delivers an output voltage of 3 V with a low dropout regulator (LDO).The chip was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC)'s 0.35-μm CMOS process,and the temperature coefficient (TC) was measured to be only 2.1×10 6/°C over the temperature range of 40-125 °C after trimming.The power supply rejection (PSR) was 100 dB @ DC and the noise was 42 μV (rms) from 0.1 to 10 Hz.

A multimode digital controller IC for flyback converter with high accuracy primary-side feedback

A digital controller IC for the flyback converter with primary-side feedback is proposed. The controller is used for adapter charger or LED driver applications. To obtain high accuracy for the primary-side feedback, a digital primary-side sensing technology is adopted, which can auto-track the knee point of the primary auxiliary winding voltage. Furthermore, an internal digital compensator eliminates the need for external loop compensation components while achieving excellent line and load regulation. The controller could output both constant voltage and constant current depending on the load current. Pulse width modulation and pulse frequency modulation are used in constant voltage mode while quasi-resonant control is used in constant current mode. The digital controller is validated by using FPGA.

New Technique:A low drift current reference based on PMOS temperature correction technology

A low drift current reference based on PMOS temperature correction technology is proposed.To achieve the minimum temperature coefficient(TC),the PMOS cascode current mirror is designed as a cross structure.By exchanging the bias for two layers of the self-biased PMOS cascode structure,the upper PMOS,which is used to adjust the TC together with the resistor of the self-biased PMOS cascode structure,is forced to work in the linear region.As the proposed current reference is the on-chip current reference of a high voltage LED driver with high accuracy,it was designed using a CSMC 1 μm 40 V BCD process.Simulation shows that the TC of the reference current was only 23.8×10 6 /°C over the temperature range of 40-120 °C under the typical condition.

Arithmetic Operand Ordering for Equivalence Checking

An information extraction-based technique is proposed for RTL-to-gate equivalence checking. Distances are calculated on directed acyclic graph (AIG). Multiplier and multiplicand are distinguished on multiplications with different coding methods, with which the operand ordering/grouping information could be extracted from a given implementation gate netlist, helping the RTL synthesis engine generate a gate netlist with great similarity. This technique has been implemented in an internal equivalence checking tool, ZDIS. Compared with the simple equivalence checking, the speed is accelerated by at least 40% in its application to a class of arithmetic designs, addition and multiplication trees. The method can be easily incorporated into existing RTL-to-gate equivalence checking frameworks, increasing the robustness of equivalence checking for arithmetic circuits.