A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm ...A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm CMOS. The charge redistribution （CR） design and an extra A E modulator for capacitance measurement are em- ployed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2. 1 mW.展开更多
文摘A power efficient 96.1 dB-SFDR successive approximation register （SAR） analog-to-digital converter （ADC） with digital calibration aimed at capacitor mismatch is presented. The prototype is fabricated in a 0.18/zm CMOS. The charge redistribution （CR） design and an extra A E modulator for capacitance measurement are em- ployed. With a 1.1 MS/s sampling rate, the ADC achieves 70.8 dB SNDR and the power consumption is 2. 1 mW.
