Design of low power common-gate low noise amplifier for 2.4 GHz wireless sensor network applications

This paper presents a differential low power low noise amplifier designed for the wireless sensor network （WSN） in a TSMC 0.18μm RF CMOS process.A two-stage cross-coupling cascaded common-gate（CG） topology has been designed as the amplifier.The first stage is a capacitive cross-coupling topology.It can reduce the power and noise simultaneously.The second stage is a positive feedback cross-coupling topology,used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA.A differential inductor has been designed as the load to achieve reasonable gain.This inductor has been simulated by the means of momentum electromagnetic simulation in ADS.A ＂double-π＂ circuit model has been built as the inductor model by iteration in ADS.The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured.The LNA works well centered at 2.44 GHz.The measured gain S_（21） is variable with high gain at 16.8 dB and low gain at 1 dB.The NF（noise figure） at high gain mode is 3.6 dB,the input referenced 1 dB compression point（IP1dB） is about -8 dBm and the IIP3 is 2 dBm at low gain mode.The LNA consumes about 1.2 mA current from 1.8 V power supply.

Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.

A 0.5 V divider-by-2 design with optimization methods for wireless sensor networks

A 0.5 V static master-slave D flip-flop （DFF） divider-by-2 is implemented with a 0.13 μm 1P8M RF- mixed signal CMOS process. Low-threshold transistors in a deep-N well with forward-body bias technology are used in the circuit. Each of the D-latch with source coupled logic consists of sensing and latching circuits. To increase the maximum operating frequency and decrease power consumption, the latching current is one half of the sensing current. The circuit optimization methods are described in this paper. The measured maximum operating frequency is 6.5 GHz and the minimum input singled-signal amplitude is 0.15 V.

A low power quadrature up-conversion mixer for WSN application

This paper presents an up-conversion mixer for 2.4GHz wireless sensor networks in 0. 181xm RF complementary metal-oxide semiconductor （CMOS） technology. It is based on a double-balanced Gilbert cell type. With two Gilbert cells it was applied quadrature modulation. Operational ampli- tiers are used in this design to improve the conversion gain under low power consumption. The mixer design is based on 0.18txm RF CMOS process. And the mixer test results indicate that under 1.8V power supply, with input frequency 2.4 - 2.4835GHz, the conversion voltage gain is 1.2 - 2dB. When the output frequency is 2.4GHz, its power gain is -4.46dB, and its input referred 1 dB com- pression point is -11.5dBm and it consumes 1.77mA current.

Design and optimization of a 0.5 V CMOS LNA for 2.4-GHz WSN application

This paper presents a low noise amplifier（LNA）,which could work at an ultra-low voltage of 0.5 V and was optimized for WSN application using 0.13μm RF-CMOS technology.The circuit was analyzed and a new optimization method for a folded cascode LNA was introduced.Measured results of the proposed circuit demonstrated a power gain of 14.13 dB,consuming 3 mW DC power,showing 1.96 dB NF and an input 1-dB compression point of -19.9 dBm.Both input power matching（S_（11）） and output power matching（S_（22）） were below -10 dB.The results indicate that this LNA is fully applicable to low voltage and low power applications.

A low voltage low power up-conversion mixer for WSN application

This paper presents an up-conversion mixer for 2.4-2.4835 GHz wireless sensor networks （WSN） in 0.18 μm RF CMOS technology. It was based on a double-balanced Gilbert cell type, with two Gilbert cells having quadrature modulation applied. Current-reuse and cross positive feedback techniques were applied in the mixer to boost conversion gain; the current source stage was removed from the mixer to improve linearity. Measured results exhibited that under a 1 V power supply, the conversion gain was 5 dB, the input referred 1 dB compression point was -11 dBm and the IIP3 was -0.75 dBm, while it only consumed 1.4 mW.

A new wideband LNA using a g_m-boosting technique

A new broadband low-noise amplifier （LNA） is proposed. The conventional common gate （CG） LNA exhibits a relatively high noise figure, so active gin-boosting technology is utilized to restrain the noise generated by the input transistors and reduce the noise figure. Theory, simulation and measurement are shown. An implemented prototype using 0.13 μm CMOS technology is evaluated using on-wafer probing. S11 and S22 are below -10 dB across 0.1-5 GHz. Measurements also show a gain of 18.3 dB with a 3 dB bandwidth from 100 MHz to 2.1 GHz and an ⅡP3 of-7 dBm at 2 GHz. The measured noise figure is better than 2.5 dB below 2.1 GHz, is better than 4.5 dB below 5 GHz, and at 500 MHz, it gets its minimum value 1.8 dB. The LNA consumes 9 mA from 1.5 V supply and occupies an area of 0.04 mm^2.