A Novel Variable Shifting Code for Test Compression of SoC

The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.

Reliability evaluation of high-performance,low-power FinFET standard cells based on mixed RBB/FBB technique

With shrinking transistor feature size,the fin-type field-effect transistor（FinFET） has become the most promising option in low-power circuit design due to its superior capability to suppress leakage.To support the VLSI digital system flow based on logic synthesis,we have designed an optimized high-performance low-power FinFET standard cell library based on employing the mixed FBB/RBB technique in the existing stacked structure of each cell.This paper presents the reliability evaluation of the optimized cells under process and operating environment variations based on Monte Carlo analysis.The variations are modelled with Gaussian distribution of the device parameters and 10000 sweeps are conducted in the simulation to obtain the statistical properties of the worst-case delay and input-dependent leakage for each cell.For comparison,a set of non-optimal cells that adopt the same topology without employing the mixed biasing technique is also generated.Experimental results show that the optimized cells achieve standard deviation reduction of 39.1%and 30.7%at most in worst-case delay and inputdependent leakage respectively while the normalized deviation shrinking in worst-case delay and input-dependent leakage canbe up to 98.37%and 24.13%,respectively,which demonstrates that our optimized cells are less sensitive to variability and exhibit more reliability.