Toward High Carrier Mobility and Low Contact Resistance:Laser Cleaning of PMMA Residues on Graphene Surfaces

Poly(methyl methacrylate)(PMMA) is widely used for graphene transfer and device fabrication.However,it inevitably leaves a thin layer of polymer residues after acetone rinsing and leads to dramatic degradation of device performance.How to eliminate contamination and restore clean surfaces of graphene is still highly demanded.In this paper,we present a reliable and position-controllable method to remove the polymer residues on graphene films by laser exposure.Under proper laser conditions,PMMA residues can be substantially reduced without introducing defects to the underlying graphene.Furthermore,by applying this laser cleaning technique to the channel and contacts of graphene fieldeffect transistors(GFETs),higher carrier mobility as well as lower contact resistance can be realized.This work opens a way for probing intrinsic properties of contaminant-free graphene and fabricating high-performance GFETs with both clean channel and intimate graphene/metal contact.

Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）. The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness （EOT） scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.

Experimental clarification of orientation dependence of germanium PMOSFETs with Al_2O_3/GeO_x/Ge gate stack

An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is （110）〉（111） ~ （100）, and the best channel direction is （110）/[110]. Moreover, the （110） device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while （100） and （111） devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.

Memory materials and devices:From concept to application

Memory cells have always been an important element of information technology.With emerging technologies like big data and cloud computing,the scale and complexity of data storage has reached an unprecedented peak with a much higher requirement for memory technology.As is well known,better data storage is mostly achieved by miniaturization.However,as the size of the memory device is reduced,a series of problems,such as drain gate-induced leakage,greatly hinder the performance of memory units.To meet the increasing demands of information technology,novel and high-performance memory is urgently needed.Fortunately,emerging memory technologies are expected to improve memory performance and drive the information revolution.This review will focus on the progress of several emerging memory technologies,including two-dimensional material-based memories,resistance random access memory(RRAM),magnetic random access memory(MRAM),and phasechange random access memory(PCRAM).Advantages,mechanisms,and applications of these diverse memory technologies will be discussed in this review.

A VCO sub-band selection circuit for fast PLL calibration

A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

Vertical‐organic‐nanocrystal‐arrays for crossbar memristors with tuning switching dynamics toward neuromorphic computing

Memristors proposed by Leon Chua provide a new type of memory device for novel neuromorphic computing applications.However,the approaching of distinct multi‐intermediate states for tunable switching dynamics,the con-trolling of conducting filaments(CFs)toward high device repeatability and reproducibility,and the ability for large‐scale preparation devices,remain full of challenges.Here,we show that vertical‐organic‐nanocrystal‐arrays(VONAs)could make a way toward the challenges.The perfect one‐dimensional structure of the VONAs could confine the CFs accurately with fine‐tune resistance states in a broad range of 103 ratios.The availability of large‐area VONAs makes the fabrication of large‐area crossbar memristor arrays facilely,and the analog switching characteristic of the memristors is to effectively imitate different kinds of synaptic plasticity,indicating their great potential in future applications.

Insight into multiple-triggering effect in DTSCRs for ESD protection

The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.