Effects of electrical stress on the characteristics and defect behaviors in GaN-based near-ultraviolet light emitting diodes

The degradation mechanism of GaN-based near-ultraviolet(NUV,320-400 nm)light emitting diodes(LEDs)with low-indium content under electrical stress is studied from the aspect of defects.A decrease in the optical power and an increase in the leakage current are observed after electrical stress.The defect behaviors are characterized using deep level transient spectroscopy(DLTS)measurement under different filling pulse widths.After stress,the concentration of defects with the energy level of 0.47-0.56 eV increases,accompanied by decrease in the concentration of 0.72-0.84 eV defects.Combing the defect energy level with the increased yellow luminescence in photoluminescence spectra,the device degradation can be attributed to the activation of the gallium vacancy and oxygen related complex defect along dislocation,which was previously passivated with hydrogen.This study reveals the evolution process of defects under electrical stress and their spatial location,laying a foundation for manufacture of GaN-based NUV LEDs with high reliability.

Analysis of Off-State Leakage Current Characteristics and Mechanisms of Nanoscale MOSFETs with a High-k Gate Dielectric

The off-state leakage current characteristics of nanoscale channel metal-oxide-semiconductor field-effect transistors with a high-k gate dielectric are thoroughly investigated.The off-state leakage current can be divided into three components:the gate leakage current,the source leakage current,and the substrate leakage current.The influences of the fringing-induced barrier lowering effect and the drain-induced barrier lowering effect on each component are investigated separately.For nanoscale devices with high-k gates,the source leakage current becomes the major component of the off-state leakage current.

Point defect determination by photoluminescence and capacitance-voltage characterization in a GaN terahertz Gunn diode

Photoluminescence （PL） measurement is used to study the point defect distribution in a GaN terahertz Gunn diode, which is able to the degrade high-field transport characteristic during further device operation. PL, secondary ion mass spectroscopy （SIMS）, transmission electron microscope （TEM）, and capacitance-voltage （C-V） measurements are used to discuss the origin of point defects responsible for the yellow luminescence in structures. The point defect densities of about 1011 cm-2 in structures are extracted by analysis of C-V characterization. After thermal annealing treatment, diminishments of point defect densities in structures are efficiently demonstrated by PL and C-V results.

Transport mechanism of reverse surface leakage current in AlGaN/GaN high-electron mobility transistor with SiN passivation

The transport mechanism of reverse surface leakage current in the AlGaN/GaN high-electron mobility transistor（HEMT） becomes one of the most important reliability issues with the downscaling of feature size.In this paper,the research results show that the reverse surface leakage current in AlGaN/GaN HEMT with SiN passivation increases with the enhancement of temperature in the range from 298 K to 423 K.Three possible transport mechanisms are proposed and examined to explain the generation of reverse surface leakage current.By comparing the experimental data with the numerical transport models,it is found that neither Fowler-Nordheim tunneling nor Frenkel-Poole emission can describe the transport of reverse surface leakage current.However,good agreement is found between the experimental data and the two-dimensional variable range hopping（2D-VRH） model.Therefore,it is concluded that the reverse surface leakage current is dominated by the electron hopping through the surface states at the barrier layer.Moreover,the activation energy of surface leakage current is extracted,which is around 0.083 eV.Finally,the SiN passivated HEMT with a high Al composition and a thin AlGaN barrier layer is also studied.It is observed that 2D-VRH still dominates the reverse surface leakage current and the activation energy is around 0.10 eV,which demonstrates that the alteration of the AlGaN barrier layer does not affect the transport mechanism of reverse surface leakage current in this paper.

Resistive switching characteristics of Ti/ZrO_2/Pt RRAM device

In this paper, the bipolar resistive switching characteristic is reported in Ti/ZrO2/Pt resistive switching memory de- vices. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament composed of oxygen vacancies. The conduction mechanisms for low and high resistance states are dominated by the ohmic conduc- tion and the trap-controlled space charge limited current （SCLC） mechanism, respectively. The effect of a set compliance current on the switching parameters is also studied： the low resistance and reset current are linearly dependent on the set compliance current in the log-log scale coordinate; and the set and reset voltage increase slightly with the increase of the set compliance current. A series circuit model is proposed to explain the effect of the set compliance current on the resistive switching behaviors.

Influence of the Diamond Layer on the Electrical Characteristics of AlGaN/GaN High-Electron-Mobility Transistors

The thermal management is an important issue for AlGaN/GaN high-electron-mobility transistors （HEMTs）. In this work, the influence of the diamond layer on the electrical characteristics of AlGaN/GaN HEMTs is investigated by simulation. The results show that the lattice temperature can be effectively decreased by utilizing the diamond layer. With increasing the drain bias, the diamond layer plays a more significant role for lattice temperature reduction. It is also observed that the diamond layer can induce a negative shift of threshold voltage and an increase of transconductance. Furthermore, the influence of tile diamond layer thickness on the frequency characteristics is investigated as well. By utilizing the 10-μm-thiekness diamond layer in this work, the cutoff frequency fT and maximum oscillation frequency fmax can be increased by 29% and 47%, respectively. These results demonstrate that the diamond layer is an effective technique for lattice temperature reduction and the study can provide valuable information for HEMTs in high-power and high-frequency applications.

The Transport Mechanisms of Reverse Leakage Current in Ultraviolet Light-Emitting Diodes

The transport mechanisms of the reverse leakage current in the UV light-emitting diodes （380nm） are investi- gated by the temperature-dependent current-voltage measurement first. Three possible transport mechanisms, the space-limited-charge conduction, the variable-range hopping and the Poole-Frenkel emission, are proposed to explain the transport process of the reverse leakage current above 295 K, respectively. With the in-depth investigation, the former two transport mechanisms are excluded. It is found that the experimental data agree well with the Poole Frenkel emission model. Furthermore, the activation energies of the traps that cause the reverse leakage current are extracted, which are 0.05eV, 0.09eV, and 0.11 eV, respectively. This indicates that at least three types of trap states are located below the bottom of the conduction band in the depletion region of the UV LEDs.

Depth-dependent mosaic tilt and twist in GaN epilayer:An approximate evaluation

An approach based on depth-sensitive skew-angle x-ray diffraction （SAXRD） is presented for approximately evalu- ating the depth-dependent mosaic tilt and twist in wurtzite c-plane GaN epilayers. It is found that （103） plane and （101） plane, among the lattice planes not perpendicular to the sample surface, are the best choices to measure the depth profiles of tilt and twist for a GaN epilayer with a thickness of less than 2 μm according to the diffraction geometry of SAXRD. As an illustration, the depth-sensitive （103）/（101） ω-scans of a 1.4-μm GaN film grown by metal-organic chemical vapor deposition on sapphire substrate are measured and analyzed to show the feasibility of this approach.

Model of hot-carrier induced degradation in ultra-deep sub-micrometer nMOSFET

The degradation produced by hot carrier （HC） in ultra-deep sub-micron n-channel metal oxide semiconductor field effect transistor （nMOSFET） has been analyzed in this paper. The generation of negatively charged interface states is the predominant mechanism for the ultra-deep sub-micron nMOSFET. According to our lifetime model of p-channel MOFET （pMOFET） that was reported in a previous publication, a lifetime prediction model for nMOSFET is presented and the parameters in the model are extracted. For the first time, the lifetime models of nMOFET and pMOSFET are unified. In addition, the model can precisely predict the lifetime of the ultra-deep sub-micron nMOSFET and pMOSFET.

Hot carrier degradation and a new lifetime prediction model in ultra-deep sub-micron pMOSFET

The hot carrier effect （HCE） of an ultra-deep sub-micron p-channel metal–oxide semiconductor field-effect transistor （pMOSFET） is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time （t）, channel width （W ）, channel length （L）, and stress voltage （Vd ） is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.

Flat-roof phenomenon of dynamic equilibrium phase in the negative bias temperature instability effect on a power MOSFET

The effect of the static negative bias temperature （NBT） stress on a p-channel power metal-oxide-semiconductor field-effect transistor （MOSFET） is investigated by experiment and simulation. The time evolution of the negative bias temperature instability （NBTI） degradation has the trend predicted by the reaction-diffusion （R-D） model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R-D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.

Distribution of electron traps in SiO_2/HfO_2 nMOSFET

In this paper, the principle of discharge-based pulsed I–V technique is introduced. By using it, the energy and spatial distributions of electron traps within the 4-nm HfO_2 layer have been extracted. Two peaks are observed, which are located at ？E ^-1.0 eV and-1.43 eV, respectively. It is found that the former one is close to the SiO_2/HfO_2 interface and the latter one is close to the gate electrode. It is also observed that the maximum discharge time has little effect on the energy distribution. Finally, the impact of electrical stress on the HfO_2 layer is also studied. During stress, no new electron traps and interface states are generated. Meanwhile, the electrical stress also has no impact on the energy and spatial distribution of as-grown traps. The results provide valuable information for theoretical modeling establishment, material assessment,and reliability improvement for advanced semiconductor devices.

Effects of stress conditions on the generation of negative bias temperature instability-associated interface traps

The exponent n of the generation of an interface trap （Nit）, which contributes to the power-law negative bias temperature instability （NBTI） degradation, and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vg and temperature T. It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vg and T. The time evolution of the exponent n is affected by the stress conditions, which is reflected in the shift of the onset of the diffusion-limited phase. According to the diffusion profiles, the generation of the atomic hydrogen species, which is equal to the buildup of Nit, is strongly correlated with the stress conditions, whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.

AlGaN/GaN high electron mobility transistor with Al_2O_3+BCB passivation

In this paper, Al2O3 ultrathin film used as the surface passivation layer for A1GaN/GaN high electron mobility transistor （HEMT） is deposited by thermal atomic layer deposition （ALD）, thereby avoiding plasma-induced damage and erosion to the surface. A comparison is made between the surface passivation in this paper and the conventional plasma enhanced chemical vapor deposition （PECVD） SiN passivation. A remarkable reduction of the gate leakage current and a significant increase in small signal radio frequency （RF） performance are achieved after applying Al2O3＋BCB passivation. For the Al2O3＋BCB passivated device with a 0.7μm gate, the value of fmax reaches up to 100 GHz, but it decreases to 40 GHz for SiN HEMT. The fmax/ft ratio （〉 4） is also improved after Al2O3＋BCB passivation. The capacitancevoltage （C-V） measurement demonstrates that Al2O3＋BCB HEMT shows quite less density of trap states （on the order of magnitude of 1010 cm-2） than that obtained at commonly studied SiN HEMT.

Electron Trap Energy Distribution in HfO2 by the Discharge-Based Pulse I-V Technique

With the rapid development of semiconductor technology, the feature size of MOSFETs has been aggressively scaled down. The thickness of gate di- electric reduces accordingly, which causes significant gate leakage current via direct tunneling. To suppress the leakage current, high-k materials are highly de- manded to replace the conventional gate dielectrics, such as SiO2 and SiON, due to the fact that its higher dielectric constant can ensure a larger physical thick- ness at the same EOT and reduce the leakage current accordingly. Among the alternative high-k materi- als, HfO2 is a promising candidate with a relatively high dielectric constant, good thermal stability and a relatively large bandgap. However, previous work demonstrated that there are large density defects in HfO2, which is a few orders of magnitude higher than that in conventional SIO2. This limits its application in MOSFETs due to the excessive low-field leakage current induced by trap-assisted tunneling, which will increase the static power dissipation in integrated cir- cuits. For theoretical modeling establishment and fast material assessment, the energy distribution of elec- tron traps across the HfO2 becomes essential. How- ever, the detailed information is still largely missing.

Low leakage 3×VDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process

A new low leakage 3×VDD-tolerant electrostatic discharge(ESD)detection circuit using only low-voltage device without deep N-well is proposed in a standard 90-nm 1.2-V CMOS process.Stacked-transistors technique is adopted to sustain high-voltage stress and reduce leakage current.No NMOSFET operates in high voltage range and it is unnecessary to use any deep N-well.The proposed detection circuit can generate a 38 mA current to turn on the substrate triggered silicon-controlled rectifier(STSCR)under the ESD stress.Under normal operating conditions,all the devices are free from over-stress voltage threat.The leakage current is 88 nA under 3×VDD bias at 25°C.The simulation result shows the circuit can be successfully used for 3×VDD-tolerant I/O buffer.

Monolithically integrated enhancement/depletion-mode AlGaN/GaN HEMT D flip-flop using fluorine plasma treatment

Depletion-mode and enhancement-mode AlGaN/GaN HEMTs using fluorine plasma treatment were integrated on one wafer.Direct-coupled FET logic circuits,such as an E/D HEMT inverter,NAND gate and D flip-flop,were fabricated on an AlGaN/GaN heterostructure.The D flip-flop and NAND gate are demonstrated in a GaN system for the first time.The dual-gate AlGaN/GaN E-HEMT substitutes two single-gate E-HEMTs for simplifying the NAND gate and shrinking the area,integrating with a conventional AlGaN/GaN D-HEMT and demonstrating a NAND gate.E/D-mode D flip-flop was fabricated by integrating the inverters and the NAND gate on the AlGaN/GaN heterostructure.At a supply voltage of 2 V,the E/D inverter shows an output logic swing of 1.7 V,a logic-low noise margin of 0.49 V and a logic-high noise margin of 0.83 V.The NAND gate and D flip-flop showed correct logic function demonstrating promising potential for GaN-based digital ICs.

A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process

An electrostatic discharge （ESD） detection circuit with a modified RC network for a 90-nm process clamp circuit is proposed. The leakage current is reduced to 4.6 nA at 25 ℃. Under the ESD event, it injects a 38.7 mA trigger current into the P-substrate to trigger SCR, and SCR can be turned on the discharge of the ESD energy. The capacitor area used is only 4.2 μm2. The simulation result shows that the proposed circuit can save power consumption and layout area when achieving the same trigger efficiency, compared with the previous circuits.