A fourth-order bandwidth-reconfigurable delta-sigma modulator for audio applications

A single loop fourth-order delta-sigma modulator is presented for audio applications. A reconfigurable mechanism is adopted for two bandwidth-based modes （8 kHz/16 kHz）. Manufactured in the SM1C 0.13μm CMOS mixed signal process, the chip consumes low power （153.6 μW） and occupies a core area of 0.98×0.46 mm2. The presented modulator achieves an 89.3 dB SNR and 90.2 dB dynamic range in 16 kHz mode, as well as a 90.2 dB SNR and 86 dB dynamic range in 8 kHz mode. The designed modulator shows a very competitive figure of merit among state-of-the-art low voltage modulators.

A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration

Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.

A single-ended 10-bit 200 kS/s 607 μ W SAR ADC with an auto-zeroing offset cancellation technique

Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows expo- nentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607/μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and- distortion ratio （SNDR） is 60.1 dB and the spurious-free dynamic range （SFDR） is 68.1 dB. The measured DNL is ±0.37/-0.06 LSB and INL is ±0.58/-0.22 LSB.

An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.

Design of a 1.12Gb/s 11.3mW low-voltage differential signaling transmitter

This paper presents a 1.12 Gb/s 11.3 mW transmitter using 0.18μm mixed signal complementary metal- oxide semiconductor technology with a 1.8 V supply voltage. This transmitter implements a high-speed transmission with 1.2 V common-mode output voltage, adopting a low-voltage differential signaling （LVDS） technique. A multiplexer （MUX） and an LVDS driver are critical for a transmitter to complete a high-speed data transmission. This paper proposes a high power-efficiency single-stage 14 ： 1 MUX and an adjustable LVDS driver circuit, capable of driving different loads with a slight increase in power consumption. The prototype chip implements a transmitter with a core area of 970 × 560μm2, demonstrating low power consumption and adjustable driving capability.

A 12-bit 100 MS/s pipelined ADC with digital background calibration

This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.

An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers. The enhancer utilizes the class-AB input stage to improve current efficiency, while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier. During the slewing period, the enhancer detects input differential voltage of the amplifier, and produces external enhancement currents for the amplifier, driving load capacitors to charge/discharge faster. Simulation results show that, fora large input step, the enhancerreduces settling time by nearly 50%. When the circuit is employed in a sample-and-hold circuit, it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB. The proposed circuit is very suitable to operate under a low voltage （1.2 V or below） with a standby current of 200 μA.