A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. T...A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.展开更多
A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ...A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ports,which greatly facilitates the application.DAC core adopts 4+8 segmented current steering structure.R-2R ladder network is used for 8 least significant bit(LSB)to realize binary current weighting and thermometer coding is used for 4 most significant bit(MSB).Return-to-zero(RZ)technology is used to expand the effective bandwidth of DAC output to the third Nyquist band.The proposed DAC has a better output power flatness and spurious-free dynamic range(SFDR).Compared to traditional DAC,measured results demonstrate that the output power of this RZ DAC is increased by 33 dB and the SFDR is enhanced by 27 dB near the second Nyquist band.展开更多
文摘A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.
基金supported by Open Project of State Key Laboratory of Millimeter Waves (K201727)Open Project of National and Local Joint Engineering Laboratory of RF Integration and Micro-Assembly Technology (KFJJ20170203)+1 种基金National Science Foundation (61571235, 61504065)Scientific Research Foundation of Nanjing University of Posts and Telecommunications (NUPTSF NY215138)
文摘A 12-bit 2.6 GS/s radio frequency digital to analog converter(RF DAC)based on 1 um GaAs heterojunction bipolar transistor(HBT)process is presented.The DAC integrates a 4:1 multiplexer to reduce the data rate of input ports,which greatly facilitates the application.DAC core adopts 4+8 segmented current steering structure.R-2R ladder network is used for 8 least significant bit(LSB)to realize binary current weighting and thermometer coding is used for 4 most significant bit(MSB).Return-to-zero(RZ)technology is used to expand the effective bandwidth of DAC output to the third Nyquist band.The proposed DAC has a better output power flatness and spurious-free dynamic range(SFDR).Compared to traditional DAC,measured results demonstrate that the output power of this RZ DAC is increased by 33 dB and the SFDR is enhanced by 27 dB near the second Nyquist band.
