A 2DEG charge density based drain current model for various Al and In molefraction mobility dependent nano-scale AlInGaN/AlN/GaN HEMT devices

We present a two-dimensional electron gas （2DEG） charge-control mobility variation based drain cur- rent model for sheet carrier density in the channel. The model was developed for the AIInGaN/A1N/GaN high- electron-mobility transistor. The sheet carrier density model used here accounts for the independence between the Fermi levels Ef and ns along with mobility for various AI and In molefractions. This physics based ns model fully depends upon the variation of El, u0, the first subband E0, the second subband El, and as. We present a physics based analytical drain current model using ns with the minimum set of parameters. The analytical resuks obtained are compared with the experimental results for four samples with various molefraction and barrier thickness. A good agreement between the results is obtained, thus validating the model.

Polarization and Breakdown Analysis of AlGaN Channel HEMTs with AlN Buffer

We have demonstrated the first carrier density model for AlGaN channel with AlN buffer using spontaneous and piezoelectric polarization comparison with experimental and theoretical results. From the results we proved that the formation of 2DEG in undoped structure relied both on spontaneous and piezoelectric polarization. The electron distribution of Al concentration (0 < x < 0.5) was measured for both AlGaN channel and barrier. Barrier thickness assumed between 20 and 25 nm for validating the experimental results. The carrier concentration was observed at the specific interface of the N- and Ga-face by assuming x1, x2 = 0. The model results are verified with previously reported experimental data.

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AIInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas （2DEG） density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering （DIBL）, subthreshold slope （SS）, delay, threshold voltage （Vt）, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize theIoff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table （LUT） approach. Circuit simu- lation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in ca- dence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the perform- ance of circuits implemented using 14 nm nMOSFET.

Flicker and thermal noise in an n-channel underlap DG FinFET in a weak inversion region

We propose an analytical model for drain current and inversion charge in the subthreshold region for an underlap DG FinFET by using the minimum channel potential method, i.e., the virtual source. The flicker and thermal noise spectral density models are also developed using these charge and current models expression. The model is validated with already published experimental results of flicker noise for DG FinFETs. For an ultrathin body, the degradation of effective mobility and variation of the scattering parameter are considered. The effect of device parameters like gate length Lg and underlap length Lun on both flicker and thermal noise spectral densities are also analyzed. Increasing Lg and Lun, increases the effective gate length, which reduces drain current, resulting in decreased flicker and thermal noise density. A decrease of flicker noise is observed for an increase of frequency, which indicates that the device can be used for wide range of frequency applications.

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addi- tion to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing independent bias control for the front and the back gates. Here a non-quasi-static （NQS） small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD sim- ulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, Cgal and Cgd2, the intrinsic front and back distributed channel resistance, Rgdl and Rgd2 respectively, the transport de- lay, rm, and the inductance, Lsd. The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The device simulation is performed with respect to frequency up to 100 GHz.