Interference Robust Channel Hopping Strategies for Wireless Sensor Networks

Due to the shared nature of the wireless medium, the performance of wireless sensor network is often limited by both internal interference and external interference. The internal interference is that simultaneous traffic activity by neighboring nodes in the same network, while the external interference is from wireless transmissions by other types of devices, such as Wi-Fi and Bluetooth nodes. In this paper, we present two channel hopping algorithms for multichannel, single-radio wireless sensor networks. The first algorithm achieves collision-free transmission environment while do not introduce extra control overhead. The second algorithm, in addition to reducing internal interference effects, reduces the external interference effects from Wi-Fi devices. Simulation results show that both of them significantly improve performance in wireless sensor network.

A distributed cross-domain register filefor reconfigurable cryptographic processor

Due to the fact that the register files seriously affectthe performance and area of coarse-gained reconfigurablecryptographic processors, an efficient structure of thedistributed cross-domain register file is proposed to realize acryptographic processor with a high performance and a lowarea cost. In order to meet the demands of high performanceand high flexibility at a low area cost, a union structure withthe multi-ports access structure, i, e., a distributed cross-domain register file, is designed by analyzing the algorithmfeatures of different ciphers. Considering different algorithmrequirements of the global register files and local register files,the circuit design is realized by adopting different designparameters under TSMC （ Taiwan SemiconductorManufacturing Company） 40 nm CMOS（complementary metaloxide semiconductor） technology and compared with othersimilar works. The experimental results show that theproposed distributed cross-domain register structure caneffectively improve the performance of the unit area, of whichthe total performance of block per cycle is improved by17.79% and performance of block per cycle per area isimproved bv 117 %.

Improved Model of Radial Vibration in Switched Reluctance Motor Including Magnetic Saturation

This paper proposes an improved method for the prediction of radial vibration in switched reluctance motor(SRM)considering magnetic saturation.In this paper,the basic modeling principle is briefly introduced,it is based on the derivation that the peak acceleration is dependent on the product of phase current and current gradient idi/dt.However,the derivation may cause errors due to saturation effect.Thus in this paper,the discrete sample data are firstly acquired based on DC pulse measurement method,by which electromagnetic,torque and peak acceleration characteristics can all be acquired.Then the entire peak acceleration characteristics are obtained by improved Least Square Support Vector Machine(LSSVM).Based on the obtained static peak acceleration characteristics,the time-varied radial vibration model is established based on superposition of natural oscillations of dominant vibration modes.Finally,a simulation model is built up using MATLAB/Simulink.The good agreement between simulation and experiment shows that the proposed method for modeling is feasible and accurate,even under saturation.In addition,since LSSVM does not need any prior knowledge,it is much easier for modeling compared with other existing literatures.

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.

Optoelectronic properties analysis of silicon light-emitting diode monolithically integrated in standard CMOS IC

Si p^+n junction diodes operating in the mode of avalanche breakdown are capable of emitting light in the visible range of 400-900 nm. In this study, to realize the switching speed in the GHz range, we present a transient model to shorten the carrier lifetime in the high electric field region by accumulating carriers in both p and n type regions. We also verify the optoelectronic characteristics by disclosing the related physical mechanisms behind the light emission phenomena. The emission of visible light by a monolithically integrated Si diode under the reverse bias is also discussed. The light is emitted as spatial sources by the defects located at the p-n junction of the reverse-biased diode. The influence of the defects on the electrical behavior is manifested as a current-dependent electroluminescence.

Steady State Temperature Study on RF LDMOS with Structure Modification

This paper is devoted to temperature analysis on power RF LDMOS with different feature parameters of die thickness, pitch S length and finger width. The significance of these three parameters is determined from temperature comparison obtained by 3D Silvaco-Atlas device simulator. The first three simulations focus on temperature variation with the three factors at different output power density respectively. The results indicate that both the thinner die thickness and the broaden pitch S length have distinct advantages over the shorter finger width. The device, at the same time, exhibits higher temperature at a larger output power density. Simulations are further carried out on structure with combination of different pitch s length and die thickness at a large 1W/mm output power density and the temperature reduction reaches as high as 55%.

Domain Coverage Metric for SoC Validation

The importance of system-on-chip （SoC） validation continues to grow with the increase of design size. An innovative domain coverage metric is proposed to measure the completeness and quality of validation approach. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that the point on or near the boundary is the most sensitive to domain errors. The coverage tool has been implemented using Verilog procedural interface （VPI） and applied to validation of SoC under design. Results show that the domain coverage can detect many design faults which statement and path coverage can not.

A noise immunity improved level shift structure for a 600 V HVIC

A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block＇s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.

A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.

A fast novel soft-start circuit for peak current-mode DC-DC buck converters

A fully integrated soft-start circuit for DC-DC buck converters is presented. The proposed high speed soft-start circuit is made of two sections： an overshoot suppression circuit and an inrush current suppression circuit. The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DC-DC converter with the proposed soft-start circuit has been fabricated with a standard 0.13 um CMOS process. Experimental results show that the proposed high speed soft-start circuit has achieved less than 50 us start-up time. The inductor current and the output voltage increase smoothly over the whole load range.

Active quenching circuit for a InGaAs single-photon avalanche diode

We present a novel gated operation active quenching circuit （AQC）. In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I-V characteristic measurement resuits of the detector. The circuit integrated with a ROIC （readout integrated circuit） is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications.

A 0.19 ppm/°C bandgap reference circuit with high-PSRR

A high-order curvature-compensated CMOS bandgap reference（BGR） topology with a low temperature coefficient（TC） over a wide temperature range and a high power supply reject ratio（PSRR） is presented.High-order correction is realized by incorporating a nonlinear current INL, which is generated by ？V_（GS） across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of0.19 ppm/°C over the temperature range of 165 °C（-40 to 125 °C）, PSRR of-123 d B @ DC and-56 d B @ 100 k Hz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.

A digital prediction algorithm for a single-phase boost PFC

A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF （power factor） with lower total harmonic distortion, and a faster dynamic response with the change of the input voltage or load current. For a certain system, based on the current system state parameters, the prediction algorithm can estimate the track of the output voltage and the inductor current at the next switching cycle and get a set of optimized control sequences to perfectly track the trajectory of input voltage. The proposed prediction algorithm is verified at different conditions, and computer simulation and experimental results under multi-situations confirm the effectiveness of the prediction algorithm. Under the circumstances that the input voltage is in the range of 90-265 V and the load current in the range of 20%-100%, the PF value is larger than 0.998. The 0.02 s without overshoot. The experimental results startup and the recovery times respectively are about 0.1 s and also verify the validity of the proposed method.

A sub-circuit MOSFET model with a wide temperature range including cryogenic temperature

A sub-circuit SPICE model of a MOSFET for low temperature operation is presented.Two resistors are introduced for the freeze-out effect,and the explicit behavioral models are developed for them.The model can be used in a wide temperature range covering both cryogenic temperature and regular temperatures.

A 140 mV 0.8μA CMOS voltage reference based on sub-threshold MOSFETs

A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from -20 to 120 ℃C. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm^2.

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons： one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon comer of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon comers at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry＇s 0.5-μm HV SOI technology.

A novel trajectory prediction control for proximate time-optimal digital control DC–DC converters

The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC-DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC-DC with the proposed prediction is about 8/μs when the load current changes from 0.6 to 0.1A.

Research into charge pumping method technique for hot-carrier degradation measurement of LDMOS

A measuring technique based on the CP（charge pumping）method for hot-carrier degradation measurement of high voltage N-LDMOS is researched in depth.The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail.At the same time,the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed.The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

The physical mechanisms triggering electrostatic discharge （ESD） in high voltage LDMOS power transistors （〉 160 V） under transmission line pulsing （TLP） and very fast transmission line pulsing （VFTLP） stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

Layout and process hot carrier optimization of HV-nLEDMOS transistor

Two layout and process key parameters for improving high voltage nLEDMOS （n-type lateral extended drain MOS） transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carder degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.