Design of a 1200-V Thin-Silicon-Layer p-Channel SOI LDMOS Device

A 1200-V thin-silicon-layer p-channel silicon-on-insulator(SOI)lateral double-diffused metal-oxide-semiconductor(LDMOS)transistor is designed.The device named INI SOI p-LDMOS is characterized by a series of equidistant high concentration n+islands inserted at the interface of a top silicon layer and a buried oxide layer.Accumulation−mode holes,caused by the electric potential dispersion between the device surface and the substrate,are located in the spacing between two neighboring n+islands,and greatly enhance the electric field of the buried oxide layer and therefore,effectively increase the device breakdown voltage.Based on a 2−µm−thick buried oxide layer and a 1.5-µm−thick top silicon layer,a breakdown voltage of 1224 V is obtained,resulting in the high electric field(608 V/µm)of the buried oxide layer.

Partial-SOI high voltage laterally double-diffused MOS with a partially buried n^+-layer

A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor （PSOI LDMOS） with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n＋-layer, which is partially buried on the bottom interface of the top silicon layer （PBNL PSOI LDMOS）. The undepleted interface n＋-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage （BV）. With the same thickness values of the top silicon layer （10 p.m） and buried oxide layer （0.375 μm）, the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance

A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.